Soldering - thermal vias under D-PAK

Your IR measurement does not show anything about the thermal conduction through the vias because there were none.

I have quoted you several times and you just turn a blind eye to it. Here it is again.

Do you want to correct this statement?

I don't believe I have made any attempts to insult you in this conversation. I am just trying to deal with facts.

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Rick
Reply to
rickman
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You called John a hacker, and accused John and me of "poor thinking processes," quibbled about approximations, yet, with the same information we have, offered no math of your own.

Like,

Of course, the misunderstanding was entirely yours, the 38 K/W and 4.7 K/W were accurate and plainly documented; nothing was fudged whatsoever.

I spent a bunch of hours doing ASCII drawings to help you understand what's pretty obvious to the rest of us at this point, and you just pecked at 'em, without offering corrections or improvements.

Hey, they're just models.

I'm not mad or anything, but that's what's happened. So some might feel that's coming on a little strong.

Cheers, (really!) James Arthur

Reply to
dagmargoodboat

I don't recall calling him a "hacker". "Poor thinking processes" is descriptive, not intended to be an insult. That was my entire point. John misinterpreted his IR data and got a poor result. Then he refuses to consider that he made a mistake.

The you are getting mixed up that I am saying there is no difference between the two locations for the vias. I have said the opposite. My point all along has been that the inner vias are not useless as John indicates. I think the recent link to a TI app note shows this clearly if you interpret the data properly. A lot of this data has been misinterpreted and that is my point.

I think you are mistaken. 38 K/W is actually 38 K/W/square, no? Your diagram was not labeled clearly and the diagram is not representative of reality. There is no basis for assuming some number of squares in series the way you show them. Ok, so we can't calculate the exact resistance, but as presented your diagram was very hard to interpret.

That is because the way I interpreted them they make literally no sense. But I did offer a fixed diagram at one point and you trimmed it out in your reply. I offered another diagram and you didn't reply to that post at all.

Clearly we see things differently.

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Rick
Reply to
rickman

Update: got the customer to do some measurements. Dissipation is about

850mW. Measured thetaJA--vertical, convection air both sides--works out to ~35oC/watt. Surprisingly low for 1 in^2 of 2oz copper.

So, it's quite safe with lots of margin--no heatsink needed. I'll add pour because I can, it's good practice, and free, but even that's laginappe. Cheers, James Arthur

Reply to
dagmargoodboat

Heck, you don't even need vias.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation
Reply to
John Larkin

I definitely need 'em -- the 1 sq. in. pour is divided between top and bottom. (I always run as cool as reasonably possible. MTBF, and all that.)

It was a good exercise--now everyone knows what the board can do, and future ambitions are appropriately limited. And s.e.d. got a real-life data point: thetaJA for a D-PAK, 1 sq. in. of 2 oz. Cu, etc.

Cheers, James Arthur

Reply to
dagmargoodboat

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