The vias aren't the dominant thermal resistance; the lateral, spreading thermal resistance on the bottom side is. A tight cluster of thermal vias, down to a local hot spot, isn't very effective. The thermals inside the array do almost nothing but slurp solder.
I said (and you snipped) that it was "a vaguely similar case."
But it illustrates how bad the lateral heat spreading is on a bottomside copper pour.
Gosh, you don't see it!
Do
I calculated about 4 K/W for James's via array. Dumping into a hot spot that probably has 10 K/W spreading resistance.
That wasn't my point. My point is that, to better cool the dpak, the vias need to be spread out, not clustered under the chip. And that fixes the solder scavenging problem, too.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
The amount of copper in the walls of a via goes linearly on diameter, but the solder slurp volume goes as d^2. So more small holes helps the solder scavenging situation.
A 20 mil via, in an 0.062 board, is just about one square, if you unroll it and hammer it flat. 1 oz copper is about 70 K/W per square.
Most metals run around 140,000 K/W per ohm!
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
The large pad on the D-PAK will normally be windowed, probably
4 "panes". The idea is to make the paste opening (the window panes) a few mils larger to allow more paste to accommodate the wicking.
As other post have pointed out, you can sometimes get solder dimples coming out the back side holes. If you need to mount a heat sink, this will cause problems.
In the grand scheme of things, stencils are not that expensive. Your board guy can adjust the stencil openings to find the sweet spot and generate a new paste layer for a new stencil.
That's a lot of vias. That pad must look like swiss cheese. What is your top layer cu thickness? 1/2 oz? Any good planes below the pad other than the bottom layer?
I'm not sure what you are saying. The manufacturing people see problems with thermal pads because the solder paste will splatter on occasion. The fix is to break the solder paste applied into a grid. I believe this is a design without thermal vias. Have you not seen this recommendation? I'm pretty sure the fab house takes my design files and uses the Gerbers for the board, but tosses the paste layer and makes their own. Heck, I have a hard time getting them to print the silk screen without clipping.
So it might make the thermal a bit worse, but it will largely mitigate the wicking problem? What numbers are you using for the plating inner and outer diameters?
I'm not sure why your copper would be better. The copper cross section is essentially the circumference times the plating thickness which would be the same for twice the number of half sized holes, no?
Yes, I believe I said I was specing the drill size, not the finished hole size. Why do you spec the finished hole size rather than the drill size? Or are you saying you are specing both?
Actually I specified a 0.010" hole size, but both fabs that have made my boards apply their +-0.003" tolerance spec and drill with a 0.013" drill. I have no reason to argue with them.
I'm curious, what do you expect your temperature drop through the board to be? Do you have an expected temperature drop across the spreader? What is your temperature difference between the spreader and the air?
I can't say I understand what you are drawing. What is "fill"? Doesn't the via connect directly to the copper pour?
The point being made by John is that there is little use to having
*more* vias in the center. Unless I misunderstood no one is suggesting there should be no vias around the outside of the pad. The question is do you just use vias outside the pad where there is no wicking problem or do you also use vias in the pad where wicking can be a problem.
My point is that analyzing this design by looking for a "dominate" thermal resistance is not useful. The temperature of the die is the sum of all the thermal drops and the sink temperature. The final die temperature depends on them all. If you can lower the die temperature a few degrees by adding more vias under the pad, that is not a bad thing.
Ok, but that does not indicate anything about what the vias will do.
"Probably" means you are guessing, right? But assuming you are right, I would say the 4 K/W is a pretty important number still since it will create a temperature drop that is about half the drop across the temperature drop of the "hot spot".
How do you get the heat into the vias from the chip....? Oh, I know, use a heat spreader on the top side!!! Wait, isn't that going to give you the same result?
In the real world, the vias can be under the chip and work fine. I have done this myself before. The details you are trying to optimize are largely irrelevant and end up having little impact on the die temperature.
I know guys who think like you and build fast cars. In the end they get stuff to work, but only after doing it wrong a few times.
I normally pepper something like that with, oh, twenty vias in the 10-20 mil diameter range. Around the periphery if possible -- avoids the problem altogether, but that's really only effective for passive cooling (copper pours, no heatsinking otherwise really).
Backside heatsinking, you'll need in-pad vias, preferably with enough solder paste to help out conductivity. But not so much that there's an excess that bumps out the other side. By capillary action in small enough vias, you should be able to get enough that the top side fillet looks good while the vias are filled, more or less just level with the bottom.
I always place vias in exposed pads (DFN/QFN, etc...), using just enough of them (diameter and count) to account for the extra solder of full paste coverage (normally, partial coverage is suggested). EPs of course are much more sensitive to float or starvation than DPAKs, of course.
Haven't had any complaints from manufacturing yet, but... you know how it is, they'll complain if there's no vias, if there's too many, if they're tented / capped / plugged, if they're not...
I could oversize the paste mask for the D-PAK tab too. That would deposit more paste. ISTM the "bars" needed to separate the "window" into "panes" simply reduce the total paste delivered. .----.----. |____|____| | | | '----'----'
Makes sense. No heatsink here, though I think, frankly, it could really use one topside. I've got to query the customer.
That, and moving some of the thermals out from under the pad are likely the soldering solution.
The layout guy's a bit of a character. But on review, it's a pretty good trade-off thermally, and for total solder-wicking volume.
I wanted fewer and bigger vias; that would've been worse.
You'd think so, but the holes only occupy ~4% of the surface area.
No, I haven't. I've been designing circuits since I was a kid, but not a whole bunch of SMD power stuff since the dawn of high-power SMD. Getting rid of the heat is a different matter than the old days, when heatsinks were de rigueur.
I don't know if it solves the hole-fill problem--I don't know what the board house's process will tolerate. I don't even know who the board house is.
We don't plate the outer diameters. :-)
0.020" finished hole, 25um Cu walls.
To a first approximation, yes. A more accurate calculation is pi * (r(outer)^2 - r.(inner)^2), which gives pi * 2r(outer)*plating + plating^2, which accounts for the difference.
So that the leaded components will fit into their through holes.
Standard over-simplified thermal resistance "circuit" diagram. Approximates the resistances to heat flow, broken down by segment.
Same as "pour". Sloppy labeling -- corrected.
Yes, but no, that's John's point. It connects to the big pour, but through a piece of unnecessary copper, namely, on the bottom of the board, the heat has to traverse from centered under the D-PAK to the edge of the D-PAK's outline before it gets to the rest of the pour. That adds thermal resistance, and unnecessarily.
John was saying I might as well move as many thermals as possible outside the pad outline. Topside, the device itself has a massive slug of copper that makes sure heat is evenly spread underneath it. Might as well take advantage of that.
When making contact to a sheet resistor, the contact resistance trends towards infinite as the contact diameter trends to zero. So we don't want a spot contact to the bottom ground pour, we want the biggest circle or square we can get.
I wish I had some friendly software to do sheet resistance calcs. But even that would be a simplification, because the heat is continuously dissipated to air across all the surfaces, and significant heat travels from the bottom pour through the FR4 to the top, where it also dumps into air.
There is serious 3D thermal software that takes everything into account, but that's $$$ overkill and I suspect the learning curve and setup is extreme. Has anybody used this sort of program?
I hack thermal breadboards and measure them, with an IR imager and with thermocouples. And after I make a real board, I measure it, too, for learning feedback.
This is pretty inexact. We generally don't know the actual copper thickness [1] and especially the via plating. Part thermal models are often fuzzy. And we don't often know the exact environment of the board, like convection and conduction to the enclosure and such, or air flow paths if there is venting or fans. This stuff is messy.
[1] I like to include test traces, so I can measure resistance and see how much copper the board house actually provided. I can TDR them, too, to see if I got trace impedances right. Via resistances can sort of be measured, too, and that translates to theta.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
This is too big. Every appnote on the subject clearly states that vias can not be bigger than 12 mils or so (it is 13 mil in TI appnotes if my dementia serves me right.) It is clearly stated that this is because of solder wicking problems if bigger vias were used.
Use 12 mils vias. No plugging necessary, just use full solder paste opening in your stencils (not spot pasting or whatever.) And do NOT tent those vias. The excessive solder will fill them nicely and surface tension in 12 mil via is sufficient to hold all solder inside without bleeding to other side.
15 mil vias are on the edge -- there is almost no bleed-through but you'll get bumps of solder on underside. Most of the time -- sometimes it WILL leak through. 12 mils is perfect size.
And do NOT tent those vias on the opposite side. It will not plug them to prevent solder wicking, won't allow proper filling with solder, and those will give out some gas/vapors/whatever that will force your chip to float and leave you with numerous voids when solder solidified.
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Once the part has reflowed completely down on the board surface, the surface tension should pull the solder BACK UP the holes to some extent, and give good wetting of the part to the pad. You may have to unsolder a few parts to assure you are getting broad wetting of the part's underside. Tinkering with the solder stencil aperture is pretty much required the first time you do something like this.
We had a real pain with a QFN. There was just a little too much paste and it would float just high enough that 1 or 2 of the pads would sometimes not solder correctly. The others would, so the chip would align correctly. Sometimes the board would just not work, other times intermittent. Making the windows smaller fixed that issue.
That 2oz Cu on the top should also help with this. Like others have mentioned, spread the heat out and then down to the bottom. Once you get out of the paste zone you could use larger vias if the real estate will allow.
It's been a while since I've worked with copper thicknesses. I had forgotten how thin it often is. I see now that with solder in the holes the thermal resistance will be much lower.
Do you mean pi * 2r(inner)*plating + plating^2
Even at an inner diameter of 10 mil and a plating thickness of 1 mil, your difference in copper cross section is *very* small, less than 5%. Isn't that rather in the noise?
Ok. I suppose there are always some through hold parts somewhere on a board. I can't think of anything I typically use that isn't a connector where the holes have enough slack that this isn't a problem. Different strokes...
Yes, the bottom layer is your spreader. Do you know what to expect for all the temperature drops? Not much point in optimizing one portion of the design if you don't know what the rest will do. Do you have target temperature drops?
That much I understand. The question is what are the segments you have drawn.
Ok, I would have understood if it was "copper pour" except that the entire R2 through R4 is the same copper pour. Seems to me the value of R3 is zero. What is the nature of R3?
That is the crux of the issue. The heat has to be spread by something. If R2 is not in the bottom copper pour, it is in the top layer copper pour. It doesn't go away by moving the vias, the order is just changed. R1-R2-R3... or R2-R1-R3...
That is not what I read. I thought he was saying just don't use vias inside the pad outline. Certainly it helps to add vias outside, but getting rid of the vias inside does not improve your situation unless you just can't figure out how to deal with the wicking. I think John is very mistaken to suggest there is no value to them. All the vias are in parallel and the spreading has to be done on one side of the board or the other.
Look at it this way. Do the chip makers provide a ring for the thermal pad? If the spreading was of no value in the middle I expect they wouldn't use a full pad.
Until you figure out your temperature drops you won't really know what is useful and what isn't.
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