It's certainly recommended by the manufacturer of pretty much every part with a thermal pad (they keep telling me I need more). I haven't seen your problem in years but if they're having a problem with it, they're likely not getting enough paste on the board or perhaps the vias are too big. There really shouldn't be that much wicking, particularly on something as big as a D-PAK.
Paste opening? You mean leave a clearance around the vias in the paste mask?
They asked we do that, but it seems the solder would just flow, wet, and wick, with less solder to do it all with. Their alternate "ask" was filled vias.
I pulled the artwork. There are actually two dozen x .020" thermals. More than I remembered, but the holes are small.
All the heatsinking's on the bottom, so tightly-coupled is good.
if you intend the pcb to bolt a heatsink on the back the wicking may cause another problem, you sometimes get little solder "dimples" where solder wicked through the vias so back side is not flat
I calculated the thermal array gives 5oC/W to the bottom layer. The voids occupy 3.5% of the surface area under the pad.
That's not a problem--I've got enough backside copper to handle things. If we cap the vias and the caps bulge up, holding the part off the board, that's a problem.
That's a lot of vias. How much power is the dpak dissipating? Is there a real heat sink bonded to the bottom of the board, or just a copper pour?
A 20 mil via through an 0.062 thick 1 oz board will be ballpark 70 K/watt. So 20 of them will be roughly 4 K/W.
The alternative is to move most of the thermal vias a bit outside the part footprint, with a little solder mask zone to keep the vias from slurping the solder.
Or add more paste.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
I calculated a lot less, about 70 K/W per hole, assuming 1 oz plating in the holes. Of course, if they steal the solder and fill themselves, it will be even less.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
They may have a point. I calculate the fill volume of the vias at nearly 8mm^3. If we cut the hole size in half and double the holes, we'd save 1/2 of that, and gain copper cross section.
I got five, you got four--you're only 20% less than my calculation.
I wrote a spreadsheet that does the math from basic principles & constants--should be pretty reliable.
An excellent point. If I could count on that, I could chop out most of the vias. I'm afraid to--after all, the board house's complaint is that they don't want to fill 'em.
Just a copper pour. I don't know the dissipation--originally it was trivial, but the customer has changed the topology and the load. I'm assuming it could be considerable.
Can't. I have room to move about 1/3rd of them, which we certainly will.
Yes.
As usual most of the problem is in the constraints, which are mostly artificial.
My understanding is that thermal pads get a divided solder paste mask to reduce the solder load by some amount approaching 50% anyway. I believe an unbroken slug of paste has problems with both gasses escaping and the part floating on the big ball of solder. I can't imagine the vias will wick very much in comparison.
You said the vias are 0.020, can you make them smaller and use more? When I was having a board made with 0.013 vias (drill size) I was told they nearly plate shut anyway.
If it's just a pour on the bottom, the theta of the vias is not too important.
The big issue will be thermal spreading. The vias in the interior of the array are doing almost no good, because they are in the middle of a hot spot. Vias outside the dpak footprint would likely be better than vias inside, because they "reach out" farther into the bottom pour.
I like to use a modest number of thermals inside the footprint, four maybe, plus some outside, 8 or 12 maybe, not too close in. But also use an inner layer pour as a heat spreader, to move heat from the inner to the outer vias.
Here's a vaguely similar case. A hot spot on the top of the board:
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Now what's interesting is the bottom of the board:
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Note the small hot spot (the strip is kapton tape, to raise the emissivity for the thermal imager.) That's terrible thermally. When the heat sink is a copper pour, spreading out the heat, using out-there vias on multiple layers, really helps.
Dump most of the central ones. They slurp solder but don't help much thermally.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
The data you post does not really support your conclusion. You are looking at a picture and drawing a conclusion without even considering the full design. The question is *not* what does the heat spreader do, the question is what do the vias do. The fact that the spreader has a 5 degree temperature drop says nothing about the temperature drop across the vias if you use more or less or where you put them.
I believe your test case does not have vias from what I can see, right?
that is without vias at all, I can't see how it is very relevant. Do you have any idea of the temperature drop through the board with vias?
Okay, found and fixed a bug. I get 99 K/W for a 0.020" hole, 3/4 oz. plating, 0.062" board. 4.3 K/W for my array. Filled with lead-free solder, 57 K/W each, 2.5 K/W for the array.
You're right, it's spreading-limited.
This thing's marginal, but I'm not allowed to change anything important.
It's hard to imagine a slug of paste sitting on via-Swiss-cheese will have a venting problem.
My handy spreadsheet says doubling the holes and cutting the size is a net small loss thermally if the vias are solder-filled, but cuts the hole-fill volume in half. The copper path is better, but the via-fill path (solder) is worse.
I hope they don't! We're spec'ing finished hole size. But, maybe we could change that for those holes, if desired.
That picture doesn't show it, but John's point is that the board's spreading resistance limits the heat launched into the bottom-side copper pour.
It's not nearly as useful to launch heat into the center under the pad, because there's extra resistance to the larger pour.
R2 | center edge bottom copper pour | to of pad .------------- .-----. Via | edge to fill | | pad |---\/\/\--*--/\/\/---*--/\/\/----*---/\/\/\/\/... '-----' R1 | of pad R3 | | '-------------
By connecting directly to the edge you get rid of R2.
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