Soldering - thermal vias under D-PAK

And that is my point. John took a small amount of info, from an example that wasn't even like the design being discussed and extrapolated claiming that there was no point in having vias under the part. That is not "understanding". Too little info, too much extrapolation and misunderstanding.

Yes, vias close to the edge of the part will do better at cooling than the vias in the center of the part. But to say they do next to nothing is not accurate or useful. If you can add vias under the part they will help cool the part and will be useful. The little info provided by John clearly shows this.

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Rick

Quit babbling and say something specific, maybe even on-topic.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

All wrong. I suggested a few vias under the dpak and a number, 8 or 12 maybe, outside the pad footprint, on a topside heat-spreading pour, with enough solder mask to prevent the outer vias from stealing solder paste.

I said that, in James' dense via array, the inner vias conduct very little heat and could be eliminated.

If you can add vias under the part they will

Except that they steal solder, which was the original issue. Since they are almost worthless thermally, eliminate most of them and add vias outside the pad area.

Once you add the outside vias, the inner ones are thermally shielded, within the hot spot, and the inner-inner ones are double shielded.

Spreading thermal resistance in the bottom pour is important.

If you disagree, present a better design.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

I have said plenty and you seem to want to no longer discuss that. I used your numbers to show that inner vias will continue to provide useful improvement to cooling the chip and you never responded.

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Rick

Yes, and that is the statement that is wrong as proven by your own data. The inner vias may not conduct as much heat as the outer vias, but they are in the same range of scale and will improve the temperature of the chip. Your own data shows this. Unless you mean a factor around 2 or 3 is "very little" that statement is wrong.

Removing the vias from the center means the temperature will rise unless you replace them with vias elsewhere.

Yes, I don't dispute that if you design the vias as large solder sucking voids they will create a problem.

Your data shows this is not accurate. Every via is a path for heat to escape and your "thermal shield" may cause a factor of 2 or so decrease in heat flow in these inner vias, but it is inaccurate to say the inner vias have no value.

--

Rick

That's true. If there's no temperature differential across a via, it's not going to carry much heat.

In electrical analogy, paralleling a high-value resistor (the via) across a lower-value resistor (the D-PAK slug) does little to lower the total path resistance (die to the environment).

In pictures, vias-under-tab...

FIG. 1

------ D-PAK tab 2.6K/W .-/\/\/\/\/\/\/\/\/\-. and posts photos of an example which

Those photos don't directly address the via question because they weren't meant to--those photos were from a series of investigations into the power capability of SMD resistors, IIRC.

But they underscored for me the horrible thermal spreading resistance of the copper pour. I'm using 2oz. copper, which is better, but still awful compared to the other thermal paths in play. Bridging over and bypassing part of that by spreading the thermal vias is a definite plus.

He showed us images he had handy of a prototype made to test thermal stuff, with FLIR images. An actual, documented prototype? I'd call that pretty rigorous.

Which would you trust more, a calculation, or an actual measurement? Which is more rigorous? And, that was just what he had handy from another task--I'm quite sure he's looked at lots of other actual products with that fancy FLIR of his. He does that.

Cheers, James Arthur

Yep. The main thermal advantage to under-tab vias is that they solder-fill, which the assy house hates, and is what got us here to start with...

Cheers, James Arthur

Where did you get your resistance numbers? They don't match the data

spot to a point well outside the hot spot which indicates a similar thermal conductivity to a group of vias which he or someone else

abnormal for an individual via. If you fudge the numbers the calculations won't show reality.

--

Rick

with ads. If

I keep hearing about G2 which is supposed to be a newsreader for a schmart phone. You might try that.

?-)

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I calculated the numbers from the copper cross sections, all listed in the footnotes above.

The drawing rather plainly shows the individual vias are 57K/W filled with solder, and therefore 4.75 K/W for a group of 12.

From basic principles, 2 oz. copper has a spreading resistance of

38 K/W per square. (If I miscalculated, please correct me.)

But if you're focusing on all that you're missing the boat.

The D-PAK tab is nearly 19x thicker than the PCB copper. It will quite obviously conduct heat from under its center to its edges far better--

19x better--than any copper pour can.

Channeling the D-PAK's heat to the center of the pour underneath it simply adds the thermal resistance of that part of the copper pour to the total thermal path.

.---------------. | .-----. | | 1 2 | A | 1 X 2 | B | 1 2 | | '-----' | '---------------'

If the goal is to get heat to A and B, it's better to start at 1 & 2 rather than X.

So, within the D-PAK's "shadow" on the bottom, it's better to use the

1,27 mm thick D-PAK tab to carry the heat to the D-PAK's edges than the wimpy 0.068 mm-thick copper pours.

Cheers, James Arthur

I don't dispute that 1 and 2 are better places to add vias than at X. I dispute the statement from John that a via at X has no value in cooling. Also John is promoting adding the vias at A and B which suffer the same top side copper layer resistance as the underside does.

Your numbers may have been calculated correctly, but they are a far way from showing the temperature drops across the board and the relative benefits of adding vias at X as opposed to not having vias at X which is the point being discussed. You lump the thermal resistance of all the vias into a single number 4.7 K/W but each one is 57 K/W. Then you show the sheet resistance of the copper as 38 K/W per square without factoring in the area and the shape. So apples and oranges.

John looked at a thermal image and decided that because on a board with no vias the temperature in a small area *appeared* to have little temperature difference there could be no heat flow if vias were added to the board under the package. Sure it is better to have vias at the edge of the chip, but adding vias at the center will still provide additional cooling in a significant manner. It is exactly the same as parallel resistors. Two 10 ohm resistors in series, the pair in parallel with a single 10 ohm resistor lowers the circuit impedance significantly and also the voltage drop for a constant current which is the analog to the thermal issue we are discussing.

--

Rick

I don't think it runs on my Blackberry 9900, to which I am very attached, for two features:

1. An excellent pointing device (like a miniature track pad) that is far more precise than the touchscreen; and
2. Unequalled data security.

I also like the keyboard, but you can get physical keyboards for some other brands as well.

Droids are worse than Windows for security, and Apples aren't very much better.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

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A and B are the ends of the pour. John's been saying to move most of the vias from X to 1 & 2, the edges of the D-PAK's tab.

I calculated the effect of a line of 12 vias in parallel, rather than clutter the ASCII drawing with 24 individual vias. What's wrong with that?

Partly true, yet all clearly disclosed in the drawing. It's more than enough to make relative judgements about thermal vias near the D-PAK. My aim here was to resolve the solder-wicking; yours was thermal re-design of this specific instance, a curiosity which I've been trying to accommodat e.

So, the bottom pour for the part I'm worried about is 1" x .5". Top pour i s the same. The board is vertically mounted, spaced above an aluminum chassi s, and has some airflow, but not necessarily directly on this board. The orig inal dissipation was So apples and oranges.

Of course adding vias anywhere helps, if only marginally. But, for a given number, moving them from the edge to the center detracts, not adds.

2 5 38K/W --+---/\/\/---+--/\/\/--+--/\/\/---...---- | | | | 57 /O You | '-/\/\/--O' | O---------' John

If there's already a 2 ohm resistance to a point, then 5 ohms extra (or, before you jump on it again, value it might be) to a further point, it's better to connect every one of your 57 ohm resistors past the 5 ohms than before it.

Cheers, James Arthur

Half a watt would be fine, but something like, say, 5 watts will get serious. But slap a thermocouple on the tab and be sure.

"Loads unknown" does make analysis more difficult.

I tested a SOT89 (Supertex DN2530 depletion fet) for power capability, and decided it would be fine at 3 watts with some reasonable copper pours.

Engineering isn't about proving how smart you are, or about showing how dumb other people are, or indeed about proving anything at all. It's about building things that work and getting purchase orders for same.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

The post I was responding to John said to move *all* the vias to outside

1 and 2 where they suffer the sheet resistance of the top side layer. My point is that he said because the bottom of the board is isothermal under the chip and the actual thermal resistance is too high in the smaller radius area, the inner vias have no useful value. I have offered him to modify this statement to say they have less use than the outer vias, but he insists the inner vias conduct virtually no heat. That is wrong.

Because you compare the numbers for the parallel vias to the number for the sheet resistivity which you graphically show as being in series several times. Sheet resistivity is not resistance.

I'm not trying to redesign anything. I am commenting on the poor thought processes being used by John and now you. Your comment above is a perfect example. You have presented no data that can be usefully compared regarding the vias under the part.

That is the issue, what is "marginal". From the data shown by John I estimate the vias in the center of the part will have no more than twice the thermal resistance as the vias outside the edge of the part. So if they can be added, I would add them.

I have no idea where you get these values. I believe the 57 you show is one via? But what are the 2 and the 5 and the 38? Are you trying to show the effect of adding one via to a board with dozens of vias already? BTW, John's point is not to move the via to another location. He says the vias have no value which means drop them entirely. If I can add a dozen vias under the pad, in your model, it looks like I would have about 5 in parallel with 2 which would still produce a useful improvement. Oh, you continue to confuse sheet resistivity with resistance. You need to figure out what value to use in place of the 38 K/W/square.

2 5 38K/W --+---/\/\/---+--/\/\/----/\/\/---...---- | | | 57 /O You '-/\/\/--O' O John

You can create any absurd model you wish. The point is that the path through vias under the pad is not *hugely* different in thermal impedance than the vias outside the pad. John says these under pad vias are useless, the numbers presented so far say they are not useless.

I realized that John was thinking about this incorrectly when he focused on the fact that the thermal imager seemed to show the bottom side area under the pad was all the same temperature with no heat flow from the center (without vias through the board). The images don't actually show the area as isothermal and the addition of vias will change the images greatly.

--

Rick

Definitely. The old rule-of-thumb was 1 sq. in. is good for 1W with convection. This is a lab environment, 40oC max., with some forced air, which adds margin.

I can't--I've never even seen the board, probably won't, don't know who even makes them. It would be an absurd situation, of course, but the customer has made mods, taken on the responsibility for their mods, and only wants the soldering problem fixed.

Naturally. I'm wary, but it's out of my hands (quite literally).

All of this is from the customer's reticence to hire. They outsource almost everything to avoid Obama-type entanglements.

I guess the accountants like it, but it complicates designing products. There's no inventory, no approved parts list, so all the parts have to be qualified from scratch for each design. Time-consuming, and adds errors.

I get a fair amount outsourced from Germany. Apparently they're even more eager to avoid hiring actual people.

I like Jerry's sig, "Engineering is making what you need from what you have" (or something like that).

Cheers, James Arthur

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If you thought John meant to move the vias to 'A' and 'B', that would certainly explain all your objections.

I never understood any of John's posts to say that. He said to move most of the vias to the tab's edges, namely, points '1' and '2'.

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You're missing what's quite obvious, getting lost in details that don't matter, possibly because you misunderstood what John posted.

The D-PAK tab is a thermal short. It's so much better than the 2oz copper we don't *have to* go any farther--using thermal vias to reduce heat flow through that thermal short is not as effective as using the D-PAK tab and the vias to jumper past part of the thermal resistance of the bottom copper pour.

I don't know how to put it any simpler than that.

I've drawn loads of simplified conceptual ASCII drawings to try and get that across, but you keep pouncing on the details instead.

Yes, the drawings are over-simplified. If you want to do a full- detail ASCII drawing in 3-D showing all the individual vias, layers and pours, we're all eyeballs.

I beg to differ. I believe I've presented more than enough for someone skilled in the art to immediately understand the merits.

I've just been trying, six different ways from Sunday, to explain that it makes little difference to the D-PAK how you shuffle the thermal vias under its tab--the tab is a thermal short. But it makes a difference to the bottom pour if you can skip over a chunk in the process, since the bottom pour's spreading resistance is over an order of magnitude higher.

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If you had the physical model in mind, there shouldn't be any confusion.

2 ohms is very roughly the half of the D-PAK tab from die to each edge. 5 ohms is *very* order-of-magnitude approximately from "X" to "1" or "2" on the pour. In retrospect the actual is closer to three squares in parallel, or 13 ohms in this analogy, not 5.

But you're far too literal. It's not intended to be an accurate model AT ALL, just illustrating, yet again, the two via-placement possibilities.

Of course.

No, showing the incremental effect of any given via.

No, actually. I've showed the heat-spread in one dimension for clarity.

Besides that, as explained by the dimensions, the pour is precisely two squares, one on either side of centerline, each 38 K/W. If I feed the square's edge with a line of thermal vias, that's a very accurate approximation, and even still is quite an irrelevant detail when comparing to a D-PAK tab that's 19 times thicker. I shouldn't have to explain this.

Okay, I give up. But it was fun, and helped clarify some stuff.

Thanks.

Cheers, James Arthur

I've asked him if he modifies this to simply mean the interior vias pass

*less* heat than the exterior vias and he is emphatic that they pass no useful heat. So there is still some question about what is "useful" heat. But that is an aside from the other issue that none of his data supports this claim. Your data is no better.

You said this very clearly, "oversimplified" to the point of being useless. Although if you change sheet resistivity to a value of resistance the diagram is very useful. What is important is the relative values of each component in the diagram. Oh, you also have to explain where your numbers come from.

Yes, your have tried, but each time you present data that has problems. You also fail to understand my point. Again, I have never said there is *no* difference between vias under the part and vias outside the part. I am saying you and John have not presented evidence that the difference makes under part vias useless. You *can* have vias in both places giving a better solution and giving your part a lower temperature or allowing a higher power dissipation.

Yes, that is an issue. But I am addressing an absolute statement by John, that's all. You can deal with the solder sucking issue in many ways. But a poor thermal analysis doesn't help that. I am just refuting some of John's ill conceived ideas.

Ok, then your drawing is wrong. John's vias do not short past the 2 ohms of the DPAK. There is only a very high resistance path to the copper pour other than through the vias which is not reflected in your drawing.

Not sure how you estimate the "squares" in the 5 ohm path because the path is radial outward from a via in roughly 180 degrees. Still, ignoring that the number of squares depends greatly on the spacing of the inner vias and how far they are from the edge. If you only place one additional via in the center that is the worst possible case and all others will be improved.

But 38 K/W is sheet resistivity, no? If that is your thermal resistance then none of this matters much since the lion's share of the temperature drop will be there.

If that is true, then the vias matter little in any case. Put them where they work best for other reasons as they will have little impact on the final die temperature.

Die 2 Edge of part --+---/\/\/---+ | Pad | \ \ / / \ Via \ Via / / \ \ | 5 | 38 +---/\/\/---+--/\/\/---...---- Pour Pour

Clearly if the vias are 57 K/W the added 3 K/W difference between the two paths is not significant and both will produce very similar cooling. Even if the 5 turns into 13 the difference between 70 and 59 is not large. So clearly your data shows the vias inside the part outline and vias at the edge are not so much different and John's claim is not valid,

"almost no good" is clearly not supported by the evidence.

Yes, it does make things more clear.

--

Rick

All along the same lines: spread out the thermal patch on the bottom pour.

In some posts he says to move the

Which is true. Verified by IR measurement, and the appnote posted here. And by common sense.

Never said that, because it's obviously untrue. The inner vias are thermally shielded, but not perfectly. But many inner vias do harm (slurp solder away from the pad) and do very little good thermally.

So there is still some question about what is "useful"

You are just another limp insult machine, like Sloman and Always Wrong, with no ability to make concrete contributions. Better to ignore you too.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation