Soldering - thermal vias under D-PAK

I've got no control or even access to the boards.

It's nuts, but that's how it is.

Cheers, James Arthur

Good idea. Thanks.

Are you using the same thickness on the bottom? I thought I read you had 1 oz there.

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Rick

Yep. Transcription error. Thanks.

It's not terribly significant. Two dozen filled 0.020" vias in parallel yield 2.4 K/W; four dozen filled 0.010 vias gives 2.9 K/W, plus a bunch of holes to drill.

The 0.010" array has lower copper K/W, but much higher fill K/W due to the halved fill volume.

The immediate problem isn't re-doing the thermal design, simply solving the soldering problem.

The original design was mine, and mass-produced. Now the customer has changed the usage and inserted a modification. I'm not privy to the requirements, I'm just solving the new soldering problem relative to the new mod.

Cheers, James Arthur

2 oz., top and bottom.

Cheers, James Arthur

FYI, John's no hacker. He's one of the most disciplined, knowledgeable, proficient engineers on the planet, and specifically expert in thermal design, from long years of practice and rigorous investigation(s).

You might want to drag up his FAQ "Notes on Cooling Electronics", posted here in SED a few years ago.

Cheers, James Arthur

July 1998, and bitter chill it was. ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

My thermal designs are a lot of guesswork and experimenting, but they all work. "Work" is sort of arbitrary, because they don't often blow things up; my thermal design errors at most result in higher than preferred junction temperatures, which degrades analog accuracy and MTBF, which are sort of fuzzy criteria anyhow.

I don't have the tools to do hard analytical thermal design, and all the required inputs aren't often available anyhow. The sorts of simple calculations that we are doing here, like calculating the theta of a PTH, are good enough. Simple experiments, and measurements on existing products, add some confidence.

Forced-air cooling is the hardest thing to predict, because air flow is peverse. We build cardboard mockups, with power resistors on heat sinks, if we think cooling is going to be critical. Hey, I'm an engineer, I'm not writing a thesus.

My last major thermal adventure was bringing down the temperature of an FPGA and a 250 MHz ADC on a small data acquisition box. I didn't want to do it (I figured and measured that junction temps were fine) but the customer insisted, something silly about the MTBF of a bunch of $1.2e8 machines. The "fix" was vias and copper pours on the PCB, and a Bergquist non-silicone therma-pad under the PCB, which dropped the board temp about 14C. I did learn some things, so it wasn't a wasted effort.

One fun thing was to program a ring oscillator inside the FPGA and calibrate that as an on-chip temperature sensor. I posted about that here and in the fpga newsgroup. Here's the board:

We make a couple of boxes that measure heatsink temp and mosfet current and voltages, and run a realtime simulation of junction temperature, shutting down if it looks too high. That lets us push the fets harder than a foldback current limit would. We've generally done that in a uP, but I recently did the same with an analog computer, also posted here. The analog was more fun... no code to grind out.

It's impressive how much effort we put into thermal design and testing.

I should expand that into a pretty PDF some day. Actually, I should hire a scut bunny, put up a good rant-filled web site, and maybe write a book. Too much to design just now.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

that seems good, but you have the same problem on the top side of the PCB btweeen the hot part of the device and the vias.

but putting some viae under the hot tab takes some of the heat through to the back side which will reduce some of the resistance

A B / / [TAB]/ / ----------------- )###||####||#||####||###) (####||####||#||####||##( ----------------------- \ \ \ \ C D

So some heat goes through C and some through B Ok I've convinced myself that'll help.

--
umop apisdn 


--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

Finally a rational voice. :)

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Rick

Most of the design issues I have discussed with John have been exactly about hacking rather than designing. This one is a great example. Here he is drawing a picture and trying to understand the working and getting a wrong answer. His original statement that I am trying to get him to discuss was,

"The vias in the interior of the array are doing almost no good, because they are in the middle of a hot spot."

He continues to insist that moving the vias outside the footprint of the part is an advantage because they are outside the hot spot and the heat will spread better. But he ignores that there is still the same hot spot on the top side of the board and posts photos of an example which doesn't even have vias and can't be considered without more info.

I'm sure John is no slouch, but he is guilty of doing a cursory examination of this design issue and I can't see where his conclusions are valid. I see no evidence of "rigorous investigation" in this case.

--

Rick

vias need

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, d

I think the point is the that top side isn't the same sheet resistance it is "shorted" by the tap which is thick copper and much lower thermal resistance

+-rtab-+-rtab-+

------------+-rpcb-+-rpcb-+------------- | | | rvia rvia rvia | | |

------------+-rpcb-+-rpcb-+-------------

-Lasse

A B / / [TAB]/ / ----------------- )###||####||#||####||###) ========================================================== (####||####||#||####||##( ----------------------- \ \ \ \ C D

A heavy ground plane works, too. Of course it's sandwiched between more FR4 but it does spread the heat around the board. This, of course, requires that the tab be grounded (it usually is for ICs). The really high power ICs have the slug up, meant to have some serious heat sinking. These also tend to be grounded, so heat sinking is relatively easy.

That's not bad. Lots of vias down to cool spots on the bottom plane, fairly low thermal resistances from the chip to those many topside vias. Add an inner-layer spreader patch if you can.

It's what I said some days ago: a few vias under the part, and a topside copper pour to more vias surrounding the part. That enlarges the thermal footprint on the bottomside copper pour, and reduces the spreading resistance, which dominated the original design.

The topside copper pour will be efficient in moving heat to the outer vias, mostly because the copper run is short and those vias will not be concentrated into a hot spot. Like this:

(regulator is lower-right in the IR image)

This worked.

This is a dpak with all its thermal vias outside the pad

where the grey is the topside pour. There's a biggish pour on the bottom, layer

4, too. The upper and lower pours also conduct heat, through the insulating FR4, into the inner-layer ground (L2) and power (L3) planes, which help spread it out to the entire surface of the board.

It's better thermally for hot chips to be inboard, but other considerations tend to push regulators towards the edges of the board.

--

John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

A bunch of vias outside the chip pad works well, assuming there are many of them and that they are close to the pad. The thermal resistance of the copper from the pad to each such via will be similar to the theta of the via itself, and there can be lots of them, each dumping into a relatively cool part of the pour on the opposite side. On a small part like a dpak, that works a lot better than having a cluster of vias under the pad and a corresponding hot spot on the bottomside pour.

Try it.

Lowering thermal resistance is just like lowering electrical resistance: the more conductive paths in parallel, the lower the net resistance. The lower the temperature, the better the MTBF of the chips.

I've done hundreds of board designs where part cooling matters. I do math, I build prototypes, I instrument the real PCBs, I measure and learn. It's been a really long time since I let a part on a PCB get too hot.

As an engineer, I just need things to work. I'm not writing a thesus that I have to defend, and I don't have the tools or the time to do a full 3D thermal conduction/convection/radiation analysis of every chip on every PC board. What I do works, and things get about as hot as I expected them to get.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

Right. The thermal pad on the dpak is thick, and will be nearly isothermal. So, on a topside pour, each of the many thermal vias, close to but not under the pad, can be tightly coupled to the chip.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

You have said a lot of things. The part of your earlier post I was disagreeing on was, "The vias in the interior of the array are doing almost no good, because they are in the middle of a hot spot."

I suppose "almost no good" is very similar to "some good" which is the reality. The images you posted actually make my point. The hot spot shown in your last image of the underside of the board from your earlier

drop *even if they are in the middle of the hot spot*. The temperature

your own images. Regardless, each extra via in the hot spot will help to reduce the die temperature.

--

Rick

I think that's true. The array in question was a *lot* of vias interior to a dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so the vias interior to that array won't conduct much heat.

Maybe we can agree on "not much good" ?

The images you posted actually make my point. The hot spot

Sure, but the dominant thermal resistance won't be the vias, it will be the spreading resistance of the bottomside copper. Adding vias outside the dpak footpring will halp a lot, and they're free, if you think about them up-front.

The temperature

Look again:

The hot spot is 38C, and half an inch away, the yellow stuff is about 32.

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John Larkin                  Highland Technology Inc 
www.highlandtechnology.com   jlarkin at highlandtechnology dot com    

Precision electronic instrumentation

You can't really substantiate that claim about the hot spot being isothermal. It shows as the highest temperature on your imager, but that simply means it is the max temp *or hotter*. Maybe the thermal imager automatically sets the range appropriately, but the resolution is poor so I seriously doubt the spot is isothermal enough to show no useful heat flow.

?

You have not shown that at all. If you want to make a claim about the "dominant" thermal resistance you need to show this somehow, by measurement or analysis. So far your analysis has been far too thin to be useful.

resistance. I'd say there is significant heat flow. But in reality this is not a useful image because there are no vias and no copper on top.

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Rick