SO14 package at 154C/W? Really?

Nope, just a really big system. The on-board bandwidth is 5 or 10 times higher--we could use twice that much off-board bandwidth.

Cheers,

Phil Hobbs

RL

Either way, it sounds like a good reason to create a ZIF connector with wiping action. 4736 pins at even 0.05 oz insertion force is no joke. And move the power to another connector. 2368 signals is a lot of signals, even if half of them are power (leaving 1184 signals).

About the top clock frequency that you can go through a backplane of useful size is about 500 MHz. The propagation speeds eat you alive, not to mention skew, especially at wide transaction widths (say 256 bits). I figure they use a multiplicity of busses, at least 1184 but not more than 2368 signals was it? And going differential gets you higher clocks but with worse skew problems. Does re-aggregating several very high speed serial signals (10,000 MHz each) back to a parallel form do the job often enough to help?

These are (iirc) 5 Gb/s lines, with forward error correction, adaptive thresholds, preemphasis, decision feedback equalization, yada yada yada. The whole thing is tweaked right to the eyeballs, but it meets a

Cute gizmos, but all that stuff costs power and latency, which is another reason for going optical. We need to get below 100 uW/(Gb/s) (100 fJ/bit), which is going to be a challenge.

Cheers,

Phil Hobbs

That's what I thought you were thinking of doing.

I did a bit of handwaving. Xiling pads have a lot of input capicatance and the pullups have a lot of slop in the specs.

The Spartan3 data sheet I just glanced at said 3 to 10 pF and 0.8 to 2.3 mA for the pullups (at 3.3V)

If we assume a pin only goes to one other pin with roughly the same capicatance and the trace is a few inches (at 2 pF per inch) that's roughly a 3:1 change between making contact and no contact. More for a long trace, less if the other pad has lower input capicatance.

I'd probably assume that the pullups on a chip are all roughly the same and run a calibration pass, and then run the real scan.

It might take more than that, say calibration on a known good board to measure the other chip and length of the trace.

Moving the power to another connector doesn't help your signal integrity.

others?

Oh yeah, doing anything large scale really fast is a serious alls to the walls type endeavor. Gets pricey as well.