Asynchronous reset timing problem

Hello everyone, I have a very basic master state machine that is clocked at 200Mhz in a virtexII-pro. It has an asynchronous reset input that comes from a push-button on the board. Code looks like this:

always @ (posedge mclk or negedge resetb) begin if (~resetb) begin state

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One solution would be to synchronize your asynchronous reset by one flip-flop with his D input connected to the VCC and his RST input connected to your actual asynchronous reset, and the Q output is your new pseudo-asynchronous reset of your actual design.


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Reply to
Laurent Gauch

The objective is to eliminate the effect of a long and uncertain delay in the asynchronous reset driven throughout the chip. One single flip-flop might help, but I would augment it with an SRL16 delay of 16 clock ticks, which effectively is free, using the LUT in front of the flip-flop. Peter Alfke

Reply to
Peter Alfke

I have always used asynchronous resets with an "asynchronous assert / synchronouse de-assert" circuit. This makes timing of the reset release deterministic and allows asynchronous assertion.

For timing analysis it is most straightforward to just synchronize the signal and feed your async flop resets with the synchonrous reset.

Reply to
Chris Alexander

There are two issues here: a design issue and a tool issue. To address the tool issue, if you are using ModelSim, you probably want to use the

-notimingchecks option. Look this up in the documentation. This will prevent setup errors from being propagated as X's. -Kevin

Reply to
Kevin Neilson

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