[snip]
>>
>> We didn't have much luck with UCLA so far. They didn't understand my
>> module specs and couldn't even solder. Had to let them go. Europe would
>> be an option but the immigration procedure is a real hassle. Plus there
>> will be an expensive international move required unless you catch them
>> right after their degree. Europe doesn't have such an extreme shortage
>> of analog guys because larger companies there are often foolish. Some of
>> them consider anyone over 40 a geezer that needs to be replaced by a
>> kid. The consequences are very visible, for example with NXP's web site.
>>
>> --
>> Regards, Joerg
>>
>>
formatting link
>
>POR really should reflect what it takes to make the chip fly, not
>necessarily some arbitrary specification. That is, logic needs at
>least a VT, the worse case of N or P. So generally a chip POR will
>have a circuit that insures you at least have enough juice to turn on
>your worse case fet. Once you trust the logic (well, at least under
>static conditions), the next step is to insure the bandgap is awake,
>generally an output something above a VTN. Throw in a timer and
>hysteresis to make sure the supply rail hasn't sagged. Stuff like
>that. Thus POR is process and temperature dependent. However, as you
>probably know, that doesn't give the customer the warm and fuzzy
>feeling. They want to see something nice and snappy that can be
>verified with a DVM.
Indeed. My latest POR had hysteresis of 3.5VT/3VT plus a delay to ensure it held "resetbar" down long enough.
POR was used only on the digital sections... analog functioned on a "bandgap ready" signal.
...Jim Thompson