Rail Splitting Chips

The small-signal AC impedance looking into the virtual ground is always fairly low, at most whatever the small-signal AC impedance of the two caps in parallel is.

The transistors just keep the DC operating point from getting too out of whack. So there's no "dead band" per se, both the small and large signal impedance looking in from the VG terminal always going to be something relatively low, assuming that the currents being sourced and sunk are << than what the transistors and associated base resistors are appropriate to provide when they turn on.

You can surely do a discrete class AB VG where the impedance looking in will be more consistent at the cost of some idle current.

On Saturday, March 11, 2023 at 12:10:21 PM UTC-5, bitrex wrote:

Why is there no deadband? The transistors BE junction barely turn on until there is already movement in the set point. This movement is exactly what needs to be minimized.

I ran a simulation, and it give the exact results I expected. I added the diodes, and that works better, but still allows some 200 mVpp in the output and uses more parts that I'd like. A voltage regulator with resistors to provide pull down current, is pretty good, but I don't like the 20 mA idle draw which is added to the 17 mA load current. Using an op amp is the best performing circuit and the smallest, and likely the cheapest, with 150 uA output ripple and 2 mA idle draw.

Here's the LTspice .asc file

Version 4 SHEET 1 2292 1252 WIRE 160 -80 0 -80 WIRE 240 -80 160 -80 WIRE 304 -80 240 -80 WIRE 400 -80 304 -80 WIRE 1088 -80 928 -80 WIRE 1168 -80 1088 -80 WIRE 1232 -80 1168 -80 WIRE 1328 -80 1232 -80 WIRE 160 -32 160 -80 WIRE 400 -32 400 -80 WIRE 1088 -32 1088 -80 WIRE 1328 -32 1328 -80 WIRE 0 -16 0 -80 WIRE 928 -16 928 -80 WIRE 304 32 304 -80 WIRE 1232 32 1232 -80 WIRE 160 80 160 48 WIRE 240 80 160 80 WIRE 1088 80 1088 48 WIRE 1168 80 1088 80 WIRE 0 96 0 64 WIRE 928 96 928 64 WIRE 1088 96 1088 80 WIRE 1088 128 1088 96 WIRE 400 144 400 32 WIRE 464 144 400 144 WIRE 512 144 464 144 WIRE 656 144 592 144 WIRE 672 144 656 144 WIRE 160 160 160 80 WIRE 304 160 304 128 WIRE 400 160 400 144 WIRE 400 160 304 160 WIRE 304 192 304 160 WIRE 672 208 672 144 WIRE 1328 224 1328 32 WIRE 1392 224 1328 224 WIRE 1424 224 1392 224 WIRE 1552 224 1504 224 WIRE 1568 224 1552 224 WIRE 160 240 160 160 WIRE 240 240 160 240 WIRE 1088 240 1088 192 WIRE 1232 240 1232 128 WIRE 1328 240 1328 224 WIRE 1328 240 1232 240 WIRE 160 288 160 240 WIRE 400 288 400 160 WIRE 1568 288 1568 224 WIRE 1088 304 1088 240 WIRE 672 336 672 288 WIRE 1232 368 1232 240 WIRE 160 400 160 368 WIRE 304 400 304 288 WIRE 304 400 160 400 WIRE 400 400 400 352 WIRE 400 400 304 400 WIRE 1088 416 1088 368 WIRE 1168 416 1088 416 WIRE 1568 416 1568 368 WIRE 1088 432 1088 416 WIRE 160 448 160 400 WIRE 1088 464 1088 432 WIRE 1328 464 1328 240 WIRE 1088 576 1088 544 WIRE 1232 576 1232 464 WIRE 1232 576 1088 576 WIRE 1328 576 1328 528 WIRE 1328 576 1232 576 WIRE 48 608 0 608 WIRE 96 608 48 608 WIRE 160 608 96 608 WIRE 496 608 416 608 WIRE 544 608 496 608 WIRE 640 608 544 608 WIRE 784 608 720 608 WIRE 800 608 784 608 WIRE 1088 624 1088 576 WIRE 0 672 0 608 WIRE 496 672 496 608 WIRE 800 672 800 608 WIRE 96 704 96 608 WIRE 160 704 96 704 WIRE 1168 704 1088 704 WIRE 1248 704 1168 704 WIRE 1440 704 1248 704 WIRE 1840 704 1440 704 WIRE 1248 752 1248 704 WIRE 1088 768 1088 704 WIRE 0 784 0 752 WIRE 496 800 496 752 WIRE 496 800 416 800 WIRE 800 800 800 752 WIRE 1520 800 1392 800 WIRE 1568 800 1520 800 WIRE 1616 800 1568 800 WIRE 1744 800 1696 800 WIRE 1760 800 1744 800 WIRE 1888 800 1760 800 WIRE 1440 832 1440 704 WIRE 1840 832 1840 704 WIRE 496 848 496 800 WIRE 1392 848 1392 800 WIRE 1408 848 1392 848 WIRE 1888 848 1888 800 WIRE 1888 848 1872 848 WIRE 1520 864 1520 800 WIRE 1520 864 1472 864 WIRE 1760 864 1760 800 WIRE 1808 864 1760 864 WIRE 1088 880 1088 848 WIRE 1248 880 1248 832 WIRE 1408 880 1248 880 WIRE 1936 880 1872 880 WIRE 1936 896 1936 880 WIRE 288 912 288 864 WIRE 1248 928 1248 880 WIRE 496 976 496 928 WIRE 1440 976 1440 896 WIRE 1840 976 1840 896 WIRE 1936 992 1936 976 WIRE 1248 1056 1248 1008 FLAG 160 448 0 FLAG 0 96 0 FLAG 464 144 Out_a FLAG 240 -80 12V_a FLAG 160 160 Vref_a FLAG 672 336 0 FLAG 656 144 Vload_a FLAG 1088 624 0 FLAG 928 96 0 FLAG 1392 224 Out_b FLAG 1168 -80 12V_b FLAG 1088 240 Vref_b FLAG 1568 416 0 FLAG 1552 224 Vload_b FLAG 1088 96 Vb1_b FLAG 1088 432 Vb2_b FLAG 0 784 0 FLAG 800 800 0 FLAG 784 608 Vload_c FLAG 48 608 12V_c FLAG 544 608 Out_c FLAG 496 976 0 FLAG 1248 1056 0 FLAG 1088 880 0 FLAG 1248 880 Vref_d FLAG 1568 800 Out_d FLAG 1744 800 Vload_d FLAG 1440 976 0 FLAG 1936 992 0 FLAG 1168 704 12V_d FLAG 288 912 0 FLAG 1840 976 0 SYMBOL npn 240 32 R0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL pnp 240 288 M180 WINDOW 0 63 33 Left 2 WINDOW 3 60 70 Left 2 SYMATTR InstName Q2 SYMATTR Value 2N3906 SYMBOL res 144 -48 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 144 272 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL cap 384 -32 R0 SYMATTR InstName C1 SYMATTR Value 3.3µ SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg="KEMET" pn="C1210C335K5RAC" type="X7R" SYMBOL voltage 0 -32 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12V SYMBOL res 608 128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 75 SYMBOL voltage 672 192 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value SINE(6 1.32Vp 20) SYMBOL cap 384 288 R0 SYMATTR InstName C2 SYMATTR Value 3.3µ SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg="KEMET" pn="C1210C335K5RAC" type="X7R" SYMBOL npn 1168 32 R0 SYMATTR InstName Q3 SYMATTR Value 2N3904 SYMBOL pnp 1168 464 M180 WINDOW 0 63 33 Left 2 WINDOW 3 60 70 Left 2 SYMATTR InstName Q4 SYMATTR Value 2N3906 SYMBOL res 1072 -48 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL res 1072 448 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 1312 -32 R0 SYMATTR InstName C3 SYMATTR Value 3.3µ SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg="KEMET" pn="C1210C335K5RAC" type="X7R" SYMBOL voltage 928 -32 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 12V SYMBOL res 1520 208 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 75 SYMBOL voltage 1568 272 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value SINE(6 1.32Vp 20) SYMBOL cap 1312 464 R0 SYMATTR InstName C4 SYMATTR Value 3.3µ SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg="KEMET" pn="C1210C335K5RAC" type="X7R" SYMBOL diode 1072 128 R0 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL diode 1072 304 R0 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL voltage 0 656 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value 12V SYMBOL res 736 592 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 75 SYMBOL voltage 800 656 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V6 SYMATTR Value SINE(6 1.32Vp 20) SYMBOL res 480 656 R0 SYMATTR InstName R8 SYMATTR Value 50 SYMBOL PowerProducts\\ADP7118-5.0 288 704 R0 SYMATTR InstName U1 SYMBOL res 480 832 R0 SYMATTR InstName R9 SYMATTR Value 250 SYMBOL Opamps\\AD824 1440 800 R0 SYMATTR InstName U2 SYMBOL res 1232 736 R0 SYMATTR InstName R10 SYMATTR Value 10k SYMBOL res 1232 912 R0 SYMATTR InstName R11 SYMATTR Value 10k SYMBOL voltage 1088 752 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V7 SYMATTR Value 12V SYMBOL res 1712 784 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R12 SYMATTR Value 75 SYMBOL voltage 1936 880 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V8 SYMATTR Value SINE(6 1.32Vp 20) SYMBOL Opamps\\AD824 1840 800 M0 SYMATTR InstName U3 TEXT 624 0 Left 2 !.tran 300m TEXT 208 976 Left 2 ;Good Regulatiion\nConstant 20 mA TEXT 472 416 Left 2 ;Very Poor Regulation\n1.45Vpp TEXT 1432 480 Left 2 ;Adequate Regulation\n200 mVpp TEXT 1512 976 Left 2 ;Great Regulation\n150 uVpp, 2 mA idle current

If one is using one rail as a voltage reference, that's significant. If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works. Common-mode tolerance is built into op amp designs, and at high frequency the capacitors handle it, while at low frequency the high differential gain dominates the tiny common-mode effect.

It is a matter of designing the circuitry to tolerate a bit of variance in the raw supply voltage absolute values, while removing the irritations that come from trying to use a negative power rail as signal ground. In the worst case, one can add positive and negative regulators after those filter capacitors.

Not sure what distinction you are trying to make by saying, "If, however, one is just using the rails for power, and all signals are ground-referenced, then it just works". The problem is it doesn't work. See my simulation in the previous post. It not just doesn't work, it doesn't work *horribly* with 1.4Vpp variation in the reference output. It's pointless.

For the price of two transistors, two caps, and two resistor it can sink or source appreciable DC current from either rail while drawing zero quiescent current. Which two caps and two resistors can't do without the bias string drawing the same DC quiescent current as the max you wanna source or sink.

Your LDO "virtual ground" can't sink current either, it's only "sinking" cuz your sense divider is pulling 20 mA all day.

Or rather, very low quiescent current. "Performance" (such as it is) doesn't change much if you change R1 and R2 to 10k.

Your circuit simply doesn't work without the addition of two diodes. I have no use for a circuit that can't maintain a reference voltage to better than 1.4V. Add the diodes and it actually works. But it's still not great with 200 mVpp variation. That would probably do for this design, but would result in crosstalk between channels and input and output, unless I use two such circuits. Far too much bother, board space and cost. At some point, adding all the components costs as much as the components. Run the simulation.

Not sure what you are talking about here. Which circuit is this, a, b, c, or d? Or did you not run the simulation?

Yes, that's why the divider resistors are sized that way, which is what I said. Did you read my post? The op amp is the optimum circuit in virtually every respect. It may cost a few pennies more than the transistor design, but the transistor design won't fit on the board, so it's essentially a no-show and the cost isn't relevant. One op amp is used for both channels with virtually no crosstalk, just 150 uVpp on the output or -85 dB.

What 'reference output' do you refer to? There's no absolute ground from a class 2 wallwart, and power rails are usually not used as reference voltages, so a volt or so variance there is no problem. Would your car's electronics fail at 12V but work normally at 13.7 V? Not an acceptable bit of circuit design, if it does. 1.4Vpp there would be within normal tolerance.

It's not horrible by any means, just... something you need to design for.

The whole point of the circuit is to create a reference point for an amplifier circuit to operate with, that is midway between ground and the 12V rail. What does "absolute" ground have to do with anything? There's no such thing as an absolute ground anyway. Ground is what you declare it to be. Here's what I said in the first post...

"I read some of the discussion on "rail splitting" and it occurred to me that there should be a market for these devices. I am working on a design that will run op amps from a single rail and I need a 6V level, that can both source and sink current."

Maybe that was not clear enough. I didn't explicitly say the 6V would be the virtual ground of the amp circuit.

Having 1.4Vpp in the reference would muck the output by 1.4Vpp. WTF are you talking about "normal" tolerance? 1.4Vpp on low voltage power rail is horrid.

LOL I'm not asking you to design any amplifiers for me. I suspect the problem here is you don't understand the application. That's always the first thing any designer needs to do, is understand the application.

If you still don't understand the circuit, please look at the LTspice file I posted. In circuits a through c, the current injected into the reference voltage is just from a spice voltage source. In circuit d, I added an op amp that is like the stage which is driving the current that winds up in the reference. This lets me measure the total current drawn by the output stage of the amp, combined with the op amp providing the reference combined. The two currents are essentially out of phase, so create what looks like a sine wave rectified with about 2 mA of quiescent current.

søndag den 12. marts 2023 kl. 09.40.48 UTC+1 skrev Ricky:

depends on what you consider to be ground

Version 4 SHEET 1 2292 1252 WIRE 160 -80 0 -80 WIRE 240 -80 160 -80 WIRE 304 -80 240 -80 WIRE 400 -80 304 -80 WIRE 1088 -80 400 -80 WIRE 160 -32 160 -80 WIRE 400 -32 400 -80 WIRE 0 -16 0 -80 WIRE 304 32 304 -80 WIRE 160 80 160 48 WIRE 240 80 160 80 WIRE 400 144 400 32 WIRE 464 144 400 144 WIRE 576 144 464 144 WIRE 704 144 576 144 WIRE 992 144 784 144 WIRE 1008 144 992 144 WIRE 1136 144 1008 144 WIRE 160 160 160 80 WIRE 304 160 304 128 WIRE 400 160 400 144 WIRE 400 160 304 160 WIRE 576 176 576 144 WIRE 1088 176 1088 -80 WIRE 304 192 304 160 WIRE 1136 192 1136 144 WIRE 1136 192 1120 192 WIRE 1008 208 1008 144 WIRE 1056 208 1008 208 WIRE 1184 224 1120 224 WIRE 160 240 160 160 WIRE 240 240 160 240 WIRE 1184 240 1184 224 WIRE 160 288 160 240 WIRE 400 288 400 160 WIRE 1184 336 1184 320 WIRE 0 400 0 64 WIRE 160 400 160 368 WIRE 160 400 0 400 WIRE 304 400 304 288 WIRE 304 400 160 400 WIRE 400 400 400 352 WIRE 400 400 304 400 WIRE 1088 400 1088 240 WIRE 1088 400 400 400 FLAG 464 144 Out_a FLAG 240 -80 12V_a FLAG 160 160 Vref_a FLAG 992 144 Vload_d FLAG 1184 336 0 FLAG 576 176 0 SYMBOL npn 240 32 R0 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL pnp 240 288 M180 WINDOW 0 63 33 Left 2 WINDOW 3 60 70 Left 2 SYMATTR InstName Q2 SYMATTR Value 2N3906 SYMBOL res 144 -48 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 144 272 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL cap 384 -32 R0 SYMATTR InstName C1 SYMATTR Value 3.3u SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 mfg="KEMET" pn="C1210C335K5RAC" type="X7R" SYMBOL voltage 0 -32 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 12V SYMBOL cap 384 288 R0 SYMATTR InstName C2 SYMATTR Value 3.3u SYMATTR SpiceLine V=50 Irms=14.1 Rser=0.00348155 Lser=0 SYMBOL res 800 128 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R12 SYMATTR Value 75 SYMBOL voltage 1184 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V8 SYMATTR Value SINE(0 1.32Vp 20) SYMBOL Opamps\\AD824 1088 144 M0 SYMATTR InstName U3 TEXT 624 0 Left 2 !.tran 300m

"My circuit"?

Does your simulation serendipitously stay balanced due to its zero voltage offset sine "load?" Will an unbalanced load, with, for instance, 100 mA pulled from the positive rail and nothing drawn from the negative rail, sink virtual ground downward? Because, for the unbalanced case, no current flows through Q2 to balance things out?

Danke,

that would just make the power supply effectively ~ +5.4V / -6.6V instead of +/-6V which is fine

I don't get to choose the ground. The 12V power supply negative rail is ground, along with the 5V negative rail and the 3.3V negative rail and the -12V positive rail. This is a daughter card on a main board. Take a look at your power rails, the 12V positive and negative (you didn't even name the negative rail). They are bouncing 1.4Vpp. Is this the sort of amplifiers that you design???

I have no idea what you are thinking.

The transistor circuit without the diodes does nothing useful. It absolutely does not provide a stable output voltage.

I guess it's Lasse's circuit. Either way, it doesn't work. It's pointless.

It has poor DC regulation, unless you regulate it. But it won't rail nearly as bad as just two caps and two resistors will if you try to draw more unbalanced DC current from that than the latter's voltage divider can support.

That is to say if regulation needs to not suck for large signals at 20 Hz as in his sim then the +/- rails created need to be post-regulated.

Like what kind of performance do y'all expect for two transistors, lol. Many applications that split a wall-wart will post-regulate the +/- rails which resolves its problems as a virtual ground at DC pretty well as far as the rest of the circuit is concerned.

Why on earth do you think the power rail needs to be regulated??? It's already regulated to 12V. The idea is to provide a regulated 6V that handles both + and - current.

Two transistors with the diodes, actually works fairly well. If the circuit were driving off a zener diode to the common point of the two diodes, it would regulate much better than 200 mV. Or the resistors can be reduced in size, but that adds idle current that is not desirable. Actually, the zener would probably not do anything better without the resistors being reduced as well. The point is the bases need some minimum current to drive the output current through the CE. The zener doesn't reduce the need for drive current, it just holds the reference voltage more stable as the base current changes. Rather than the resistor currents changing, the diode currents change, driving the zener.

maybe in your application

if you need a reference that can sink and source, not a virtual ground then only thing that will work is two resistors and an opamp

What does the variance of power rails do to a transimpedance amplifier? Nothing, really. There's an input current, an operational amplifier, and a resistor in feedback... as long as you can take out a signal wire and make a ground connection, the power solution with two transistors DOES work. There's no significant problem with power rails there.

If power rails 'bounce', so what? In most of my work, a bunch of boxes all route signals for various operations, and sometimes I want a variant of one of those boxes... so a single-voltage wall wart and a few parts go into the new unit.

It certainly does something useful; that TIA won't have a lack of power. What OTHER requirements you might want to satisfy, we have no clue to.