Flicker noise tutorial

Interesting paper, thanks. I haven't been keeping up with RF CMOS design for the last dozen years or more, since I lost touch with most of my IBM Watson colleagues, so this is a nudge in the right direction.

Focusing on the asymmetry of the waveforms as the point of entry for flicker noise upconversion sounds about right, once you've got rid of the FET tail current source and the varactors.

To upconvert low-frequency stuff, you need to have a mechanism for the phase shifting effect of slow current changes not to cancel out on alternate half-cycles, so waveform asymmetry is pretty well it.

FET switches really only have Johnson noise, so switching resistors in and out to compensate for process, voltage, and temperature (PVT) shifts is a cute idea.

I'm less clear on why replacing the varactors with a bunch of caps and switches is a win, but apparently it is, at least from a flicker noise POV. Sure seems like a lot of gingerbread to hang on a 28 GHz tank circuit!

Cheers

Phil Hobbs

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Ahmmmmmmm..... and...... er.....well.... I know a tad about low phase noise oscillators..... :-)

The H-L "theory" is proven false. It simply doesn't work. Its assumptions are simply wrong.

I have a full detailed account as to why here:

Fundamentally, H-L fails, intrinsically, whenever there is a nonlinear capacitor, which is, essentially, in all circuits.

The key paper by Alper Demir, Bell Labs, showing why the H-L technique is toilet paper is in the references:

"… The right-hand-side (RHS) of the differential equation (13) for the phase error is nonlinear. Thus, one can not use superposition to calculate the phase error due to several perturbations, i.e., one can not calculate the phase errors due to two perturbations separately and then sum them up to obtain the phase error due to the two perturbations applied at the same time."

and

1 A. Demi1, with reference to the HL model, mathematically proves and states:

1.1 Is the orthogonal decomposition valid in general?

1.2 Even if it is not strictly valid, can it provide approximately correct results and intuition for practical oscillator designs?

1.3 We show that the answer to both questions is negative.

1.4 ...it can predict results off by as much as 50 dBc/Hz.

The key statements being from:

This paper explains in more simpler terms exactly why symmetrical circuits can generate up conversion and why time variance is not an explanation for up conversion.

The technique Demir development to correctly calculate phase noise was incorporated into the Mentor Graphics design suits when they purchased Berkely Design

Its simply astounding that a paper published in 2021 in the IEEE is presenting such erroneous twaddle.

.and... for the removal of doubt.... I have been an TCXO/OCXO oscillator ASIC designer for a major player in that space for 15 years... :-)

Kevin Aylward

SuperSpice Simulation - Electronics - General Relativity

All up-converion requires is a non-linear capacitor. It don't matter if the waveform is symmetrical, explained here:

CMOS switches have significant 1/f noise, even when notionally having no "dc" in them. Its a major problem in the design of LN oscillators.

The current in them due to the AC signal constitutes an effective dc bias current that generates the 1/f noise

For example, the Cadence Spectre simulator models this very accurately.

I wont repeat what posted as a reply to the original post, however... :-)

Using selectable fixed caps instead of having wider varactor control is easily explained.

All noise, whether 1/f or flatband applied to a varactor directly causes frequency modulation. Its a disaster.

If all tuning is done by the varactor, than one needs a wide pull range, that is a large K gain modulation constant of the VCO

If the tuning is staggered by fixed capacitors than the modulation constant can be made less, by design, thus the frequency modulation is minimised.

Kevin Aylward

- General Relativity SuperSpice Simulation - Electronics

I make triggered LC oscillators as the timebase for delay generators. I want my varicap to have a narrow pull range, just enough to stay phaselocked over temperature, like +- a few hundred PPM, to keep phase noise down. Varicaps are horrible capacitors!

So at powerup I center my oscillator with a digital cap.

PEREGRINE PE64907MLAA-Z

seems to work great. I haven't investigated what might be the FM contribution from any non-ideal behavior of the digital cap.

Yes.

I'm using mosfet caps. Below 0V they crap out.

Fabs don't model them well. Current one from the Fab has the temp co with the wrong sign. It don't work like one would naively expect from theory.

What I have discovered after running 10,000s of phase noise simulations and comparing to physical measurements, is that it is simply impossible to pencil and paper phase noise.

A divide by 2 gives a hump in the flatband. A divide by 3 gets lower flatband phase noise than a divide by 4, sometimes.....

Its all darkness.....

- General Relativity SuperSpice Simulation - Electronics

Well, it's complex enough that I can justify not using theory. Spice, guess, prototype.

The worst capacitor is the FR4 PC board. Good parts placement and cutting holes in planes helps with that.

My triggerd oscillators have an inductor (that's a whole nother story) and one good NPO cap, then a padded NTC cap, then the digital cap, and finally the varicap. Labor intensive to prototype and test, especially tempcos. The oscillators are phase-locked to an XO in under a microsecond after startup, so low frequency phase noise is not an issue.

I played with coaxial ceramic resonators, which should be much better than LCs, but there were practical difficulties. I might try again.