And there are places where it's irrelevant, or flat wrong.
I generally use 4 caps per supply, topside, maybe 0.2 inches away from the edges of the chip, with an internal plane or hefty poured island per supply voltage. Near the corners of the chip is good to minimize interfering with topside trace routing, but exact location doesn't really matter.
On a multilayer board with proper power pours, that's actually hard to do. Just keep the power:ground dielectrics thin.
Yes, I have Johnson's book, and indeed it is useful - but I have come across situations which it does not really answer.
Simple example - FPGAs require lots of decoupling caps. For my prototype boards I put the caps on the underside of the board and everything works. However, this costs more in production, so the pressure is to move everything to one side. Peering at other boards I see that it is quite common to end up with a ring of bypass caps around the fpga - but space is tight there and such a placement will inevitably increase trace lengths. I guess that one answer is to have more (perhaps partial) power planes, but that increases the board cost ! Right now I do not have a good metric for deciding which route to go - perhaps I have to build a board that doesn't quite work to learn what the limits are !
In the end, if a book provides one simple idea or fact that removes a respin, it has paid for itself many times over.
Oh, and they want the board to go twice as fast ...
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I read in sci.electronics.design that Dave Garnett wrote (in ) about 'Opinions on High Speed Design Book ?', on Wed, 16 Mar 2005:
The problem with trying less than 'perfect' bypassing is that your trial board may work but you have no way of determining how near the bone it is. I'd go for your best solution, and justify it on the grounds that you don't want to find another solution is 'not quite good enough' when you are in production. Especially if the manufacturer 'improves' the device you are trying to tame.
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
LMAO! It says, btw "An interesting consequence of this connection is that an inner-layer trace radiates no more or less than an outer layer trace. THIS IS PARTICULARLY TRUE FOR TRACES NEAR THE EDGE OF THE BOARD"
and one I violate all the time. Mostly because ground is the reference, and as long as I have enough noise margin I dont care a fig how wobbly Vcc gets.
not just contentless, but meaningless too. Why stop there: "combining 2 or more gates in one system without considering the system design consequences is not a good idea"
Hey, lets abridge it: "Not considering the system design consequences is not a good idea"
"some semblence of understanding is required"
here I dont quite get your complaint. its all about considering (and minimising) the total inductance of the physical loop around which current flows.
But fig 9.11 WILL function properly at high speeds - it will ring like a SOB, which is the proper function of such a physical construction.
So all we need to do is cover it with a thin layer of pvc, to avoid "exposure" eh? especially those nano-inch exposed wires :)
Perhaps he was using Roberts special abacus, and mis-counted the number of beads.
I would argue that:
1) its a damn good start
2) if you read and understand it, it can function as its own bullshit detector.
3) compared to, say, Tsaliovich's book on cable shielding, its a joy to read
4) compared to, say, anything ever published by TAB books (or "authored" by Irving Gottlieb or Randy Sloane), it contains useful information with enough formulae and references to point you in the right direction
How about p.376 "every clock oscillator contains a very fine high-frequency amplifier"
what, extremely thin? Shitty clock bricks, by definition, have shitty hf amplifiers....