Converting High Rise Time clock to Low Rise time clock - Chellenge!

Any modern FPGA or CPLD will give you a (lightly loaded) rise or fall time below 2 ns. Just stay away from the museum stuff. Peter Alfke =================================

What did you buffer the clock with? If you use any sort of TTL or CMOS inverter, buffer or gate, it should sharpen up the rising and falling edges. You could even run the clock through the CPLD if you have two spare pins, one input (not clock) and one output. Just have output := input.

You may not get a 2 ns rise time depending on the type of device you use for a buffer. A faster logic family normally has a faster rise time. Check the data sheet. If you are going through any standard logic device as a buffer and you still have 40 ns rise time, there is something else wrong, like maybe the scope you are measuring it with?

Or the probes? I've made myself a pair of otherwise-not-too-good probes I use for high speed stuff: one meter of RG178*; On the scope end it's terminated with 50 ohm in the plug, on the measurement end there's 950 ohm in series. They have 1/20 gain and low impedance, true, but they've proved to be far 'truer' than anything else I've used when soldered to the target (100 ps risetime with no ill behaviour), even Tektronix' tip-grounded probes.

Do NOT use a spiral-cut metal film resistor as series resistor. 4*240 ohm

/Kasper

This bloke's published some good stuff. Check out

cheers, Syms.

Maybe your scale is off?

-- glen

gain

anything

This technique is described in "High Speed Digital Design, A Handbook of Black Magic" by Howard Johnson. A good book to have for general high speed digital work.

Nial

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board