This afternoon I simulated a cascode, silicon nitride on the low side, under a SiC fet, EPC and Cree models. The Cree gate was held at +20V.
On turnoff, the SiC source flew up to +50, so I added a schottky diode
It seems to work, but might be too tricky. I'll just use a screaming gate driver into the grounded SiC part.
Pity, because the GaN just needs a few volts of gate drive.
Somebody makes an integrated cascode, mosfet on the bottom, SiC above.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Dang, I wish I had 10 ns!
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I drew the RIS-764 with the regular schematic package for Altium Designer pcb CAD. The book drawings are made/finalized in Adobe Illustrator.
The EU did the ban, are the fasteners available there?
--
Thanks,
- Win
The buffer is there so I can make 600V pulses at a 5MHz board rate (two cards are interleaved to get to 10MHz). At this rate the driver is toast, so the two sot-89 transistors and the gate resistors handle most of the burden. The SiC MOSFETs have low gate capacitance, but you can't get around P = C V^2 f, where f = 10MHz.
--
Thanks,
- Win
We've been researching really fast gate drivers for SiC fets. I have the eval board coming for the TI SMG5200, which might work if I booger the bootstrap some. The IXYS IXRFD615 should work at abs max voltage, but it's big and expensive and might use a ton of power at MHz rates. The Peregrine thing might work but the data sheet is scary.
Littlefuse just bought IXYS (!) and, after an acquisition like that, the bean counters sometime kill off products. I can't imagine what a fuse company will do with IXYS.
I might have to make my own gate driver out of parts. I need speed.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Offloading the dissipation from the driver makes sense. My rep rates are low, so, not a consideration for me.
The driver's spec'd at 4A coming and 6A going on its own, about
4x what I'm actually using anyhow.As I mentioned to John, I think my FET may be internally Miller limited--halving my 20 ohm gate resistor didn't seem to make any difference, speed-wise. The one experiment's not definitive though--there may be other factors. I may dig into that some day later.
Cheers, James Arthur
Tell me is SiC really much faster? I looked at SiC fet C2M0280120D and an Si mosfet STP4LN80K5 and Si fet has lower capacitances, for example C=122pF against 259pF. Besides Si fet takes +-30V gate voltages and your are using SiC fets close to its absolute maximum values.
If you say SIC is faster then ok, but there is not much room for errors if its absolute maximum ratings are really absolute max.
You're kidding, right? That's a mouse versus a wildcat. The STP- doesn't even do 1200V, and it's 2.1 ohms. The C2M- is 0.28 ohms and 1200V. That's
1.5 times more voltage, 7.5 times less Rds(on), and only 2.1 times more Cin. Note by the way, the SiC requires 2-3 times more gate drive swing. That still gives a figure-of-merit for SiC more than double for Si. No contest.Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
I had to go read about SiC.
George H.
There's also stuff like this,
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
Nice, weird to have an ultra precise mirror on some lab jacks though.
George H.
Nice, weird to have an ultra precise mirror on some lab jacks though. ========================================================
More like terrifying. I've never been impressed by the stability of any labjack, and just the thought of one of those rocking a bit and the mirror tipping over onto the floor would keep me from having any part of it :-).
-- Regards, Carl Ijames
It's not, it's on a spindle (about mid way between the jacks allowing for perspective) not sure what the jacks are there for, perhaps they were used for support while bolting it to the spindle.
-- This email has not been checked by half-arsed antivirus software
GaN really is much faster than Si. I've never used SiC myself.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
I was looking at SiC (and GaN) avalanche photodiode arrays for UV detection just before I retired from work. Unfortunately I timed out before I could take it any further. Another application for these materials.
Brian
-- Brian Howie
I wish there were some 1200 volt GaN power fets. The SiC things need gigantic gate drives. So the proper use of GaN is as gate drivers for SiC.
The gate drives are around
0.7 volts for phemts5 volts for GaN
30 volts for SiC-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
The schottky clamp sounds kosher to me, but in my case I suspect I'm Rg-limited. If so, cascoding doesn't help. If ever needed, I think I'd go faster by over-voltaging the gate drive for a spell.
Another possibility, not yet excluded, is that my FET is fully on and acting as a constant current source during the transition times.
Cheers, James Arthur
Cascoding looks interesting, but I think it's too tricky and risky for my application. Might blow out the gate. It makes more sense to ground the SiC source and build a ferocious gate driver. No commercial gate driver looks good for my application, making a very fast pulse. One of the giant, expensive blade-packaged IXYS things comes close.
Internal Rg is insane for some SiC parts, enough to make them useless at any interesting speeds.
D-S capacitance is a problem with the cascode. And (badly modeled) body diode behavior.
This stuff is difficult enough to be interesting.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
This seems odd; which gate gets blown out? And, why? The cascode seems OK at any reasonable slew rate. High slew currents means another kind of nightmare to me, inductive coupling to the surrounding wiring. High dV/dt doesn't do much good in a power circuit if it doesn't shift high current.
The upper one, the SiC.
And, why? The cascode
The SiC source flies way positive when the lower GaN turns off. The SiC gate is presumably held at something like +20 DC.
For reasonable slew rates, just stick to mosfets. I want unreasonable slew rates.
Switching slow is easy.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.