Ping John Larkin - SiC FETs

Oct 23, 2023 Last reply: 2 years ago 4 Replies

I have not finished watching this but I will give you the link anyway:



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Concerns degradation of SiC FETs under pulse conditions. I hope this is interesting for you. (or anyone else, for that matter)


Interesting, thanks. How long before we see driver chips with built in gate leakage monitoring I wonder?

piglet

I'm pretty sure that you know that I am not even nearly qualified to answer that question. I can't even speculate on it.

Tests on two devices at two different temperatures is largely meaningless.

The presenting the full results might make more sense.

RL

EPC employs pulse testing to determine reliability.

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RL

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