Mains voltage zero crossing detector with optical isolated output

And I just looked over last Fall's chip design... 3.3V/300uA comparator, rail-to-rail input, CMOS logic output... 2ns prop delay... pretty slow... gates on this process are ~100ps. (Keep in mind, no external loading... just driving internal logic... output load can be a killer.) ...Jim Thompson

Er - feeling a bit thick at the moment (not an unfamiliar sensation, having read your book...). Could you explain?

You mean connecting a schottky between the signal input and a buffered copy of it?

Yup. The diode goes away until something rails. I usually use two, e.g. a BAT54 dual, connected between the signal and a supply. Driving the centre tap gets rid of the leakage and most of the capacitance, but you still have to deal with (a) the Johnson noise current of the zero-bias resistance of the diode, and (b) the noise of the bootstrap differentiated by the diode capacitance.

Cheers

Phil Hobbs

That's one input versus the reference voltage, is it not? What if you plot differential output versus differential input. I didn't design any pieces (that I know of) of the FIN1101, I did circuits for the FIN10xx series, for which I still have the drawings. In that series the "reference" is _only_ related to output common-mode.

The FIN1101 data sheet says, "It can directly accept multiple differential I/O including: LVPECL, HSTL, and SSTL-2 for translating directly to LVDS.", so the reference shouldn't be involved... unless you are using with a single-ended input?

The data sheet is confusing, does the FIN1101 have hysteresis? If it does, you be "fooked" for using it as a comparator ;-) ...Jim Thompson

Aha, I almost posted that point. (Really! I spent a lot of time last year investigating that behaviour for various schmitt trigger chips and opamp alternatives, see my thread "schmitt buffers" from last year. So I am very familiar with it now!).

It is a valid effect to bring up. Don't know if it is enought to kill the circuit, I think you have the mains cycle sweeping through the high-current region quite quickly, so you only get a pulse of higher supply current for that short time (just like you already have driving the optos). There might be problems if the mains turns to DC there somehow but then the capacitative supply voltage dropper won't work either...

It is the + input voltage, relative to the - input voltage, for the outputs to be equal. In other words, it's the differential input error versus input common-mode voltage. It looks a lot like the similar curve of many r-r opamps, ones that transition from a pnp to an npn differential pair as the common-mode voltage changes.

Jonathan, in his application, considered the + input to be his signal and the - input (from a dac, usually) to be the reference.

What if you

That's gain, which I assume to be large. Since the output will drive another LVDS device, in our case the LVDS input of an FPGA, gain can be assumed to be infinite.

I didn't design

I don't think it has hysteresis, but that wouldn't matter in our apps, where we are usually detecting some trigger point on a rising edge. These parts work great for us, used thousands so far in multiple designs.

Did you design hysteresis into your LVDS designs?

OIC. I could see it got rid of the capacitance, but I did not see much advantage since you have added another opamp inputs worth. But it gets rid of the leakage too, which could be important in an integrator...

Thanks,

Nope. They are, for all intents and purpose, just differential amplifiers with an output-side common-mode reference. ...Jim Thompson

How is an HC04 any better in that respect?

The schmitt gates usually have less shoot-through current than equivalent non-schmitts. A non-schmitt will get hot if the input is in the crossover region; a schmitt usually won't.

Here are some actual curves of Icc in the transition region:

about half a mA at 5 volts supply.

In the ZCD, the signal sweeps through the transition region quickly, so the shoot-through current will average low in normal operation.

There is a cap value that minimizes - nominally zeroes - the phase shift. Not bad for three parts.

Keep in mind I ran the

The other difference is that you are used to using dozens, or hundreds, of parts to perform a simple function. "A whole bunch of extras" as you put it.

With the cap-coupled feed back, you get "snap" just as soon as the output begins to lift.

It _is_ possible to do hysteresis without a current bump. I did it in the USB to CMOS level shifters for Intel.

With the feed back it doesn't sit in that region. In the 'HC14 an internal inverter stage is the culprit.

That's different than I've measured... I've seen ~5mA, on a TI part. Maybe National fixed it along the way as I did on Intel's USB?

Is that a production value, or a tweak? Suppose the two opto-couplers don't match?

Yep. But modern CMOS is so small, that guaranteed function comes at a very small price. ...Jim Thompson

haha but not when it is at virtual earth anyway. A schottky to ground does the same thing! Clever idea for other applications though.

But the output does not begin to lift until the input gate has already gone through its transition region does it?

Schmitt triggers made from opamps seem to do it (in my testing).

Right. It's no different from a gate with internal schmitt feedback, except that it's not designed to work in its linear region.

Everything moves at once. An 'HC04 is actually 3 inverters in cascade (only the 'HCU04 is a single inverter). So it's threshold, threshold, threshold (all transistors on a single chip, so matching and tracking is superb), output moves ever so little and "swoooosh" ;-)

Works even better on an ASIC, because, internally, there's no ESD to "snuff the snap". You can also make very stable oscillators that way that are _not_ VDD sensitive.

Yep. In my nether world I do this quite nicely with comparators driving an RS-flop...

...Jim Thompson

Hmm, my understanding was the current excess was due to simultaneous conduction in the input transistors?

There _is_ overlap current which can be substantial and lengthy with a slow ramping input. However, as soon as the output moves _at_all_, the AC coupled hysteresis does its thing.

...Jim Thompson

But that reduces the average cross-conduction by only 50%, no? The input has to cross half the transition region before it gets to the point where the loop gain is enough to make the output snap.

Cheers

Phil Hobbs

That's obvious. You can say that about the HC14 type, too. The problem is that it ramps up to the full shoot-through current *before* it snaps. In your case of two levels of HC04, a lot of shoot-through will happen before it snaps. Like, six gates' worth.

And the two-level circuit with external feedback *can* propagate ugly glitches before the hysteresis kicks in. There's a lot of delay in the forward path.