Mains voltage zero crossing detector with optical isolated output

Well said :)

Jamie

Oh please not the students take note thing again. Can't you just make your point straightforwardly? Larkin does.

So did JF, until he started making out that every mistake he posted was done to be "in the style" of Larkin, (Yeah right. Will have to remember that for next time I make a complete tit of myself on usenet).

Anyway, there are some interesting issues brought up that I would actually like to know the answer to.

For example is it in fact OK to drive small amounts of current into cmos logic ESD diodes or not?

And is the answer different for the positive and negative directions? (i.e. clamping to ground or vcc).

I gather it causes problems with (some?) A/D multiplexers but have not heard of issues elsewhere. Can it mess up the other inputs or other gates in a package perhaps? What about for, say, opamps?

Your intense interest is, well, Freudian.

It causes pain with some parts, others are fine with it. Look in the spec, it's often buried in there somewhere. Xilinx, for example recommends this for clamping 5V signals, at least on some earlier parts. It causes a lot of linear parts grief.

I would *guess* that if it causes problems with a part, either direction is a problem, though thinking about it a little more, I have seen some specs that allow use of the lower diode but say nothing of the upper. The bottom line is that unless the spec says it's OK, I wouldn't do it.

Opamps are one device I'd *never* go outside the rails, unless it was specifically sanctioned by the manufacturer. Opamps are squirrely enough about high differential voltages (they're intended to be used as opamps, not comparators) without going outside the rails. I don't like using them as comparators anyway.

There's a trick for resetting integrators that involves flipping the op amp's rails upside down via current-limiting resistors. The monolithically matched input and output diodes function like a diode bridge and zero out the integration cap. (I forget where I heard about that one--I think Pease mentioned it someplace.)

Cheers

Phil Hobbs

It displays an interest.

It was wrong. I was trying to get some of the sycophants to actually stop and think. Obviously I failed.

Really ??

I'm never comfortable with more than a few _DC_ mA, particularly in Analog/Mixed-Signal parts. Some digital parts claim 20mA is OK but, again, that's transient... and relies on AC-coupled (gate capacitance) disconnects and "body snatchers"... I just learned of the value of that gimmick ;-)

Analog parts with lateral PNP's (aka SCR's-to-be :-) are more sensitive to positive rail. Though I can think of some scenario's where negative rail ESD current flow could cause issues.

The real problem is that ESD design is an art, NOT a science. Some ESD structures are excellent with disconnects to kill parasitics (as in Moto/ON-Semi 'HC' logic), some are just diodes and lots of prayer.

Some analog switches can do nasties. With OpAmps, it's usually the common-mode range that screws you up... like some brands of LM324. ...Jim Thompson

I'm not sure he has any points. If he does, he never reveals them.

Just say ITSOL after every mistake!

Depends on the part. HC logic usually has specs for allowable ESD current, with numbers like 25 or 50 mA. There are two hazards: outright diode/metalization damage, and SCR latchup.

The original CD4000 parts were notorious. A tiny spike of current into an esd diode would set off an SCR latchup, and short the power supply, frying the chip if enough supply current was available. CD4000B was a lot better.

Many linear and mixed-signal parts can mess up or latch up if you drive pins past the rails. Most analog mux's will mess up if you go a little past the rails, usually from series pass fets turning on, not so much ESD diode conduction.

LM324/339 types go nuts if you go a little below ground. LM35/45 types like to latch up. We have one TI dac that has to be surrounded by schottky diodes to be reliable; that's a power supply sequencing/latchup issue.

Longterm, there is the possibility of electromigration damage to the very thin conductors in an IC. That takes a lot of integrated current to happen.

I think the problem in the Xilinx parts is danger in damaging some very thin oxide layer from too much voltage.

In some dual/quad opamps, there are shared current sources, and railing one section of the amp will mess up others. Again, the dreadful LM324 is the poster child for this pathology. It makes a really bad comparator. The dirt-cheap bifet (LF347 type) opamps make pretty good slow comparators; it's hard to find or afford official fet-input comparators.

And the CMOS ones are all dog-slow micropower things, mostly with really wimpy drive. (Anybody got a good CMOS comparator to suggest?)

Cheers

Phil Hobbs

And third, outright goofy behavior.

They recommend the use of the ESD diodes, though. As long as the manufacturer is OK with it...

Opamps usually make crappy and expensive comparators. I avoid it if at all possible.

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I like to use LVDS-to-CMOS receivers as comparators. They get down to around 2 ns prop delays, sub-ns output edges, work rail-to-rail, and are dirt cheap. They do have large specified max offsets, like 100 mV maybe. Jonathan, one of my guys, has some actual offset measurements on some parts.

FIN1101 is LVDS in and out, has a prop delay of 1.1 ns, makes a good comparator, and costs about 75 cents.

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Thanks. It has 20 uA maximum input current, though, and I'd like something more FET-like.

(I almost wrote FET-ish, but that wasn't what I meant at all. Waving dead chickens over circuits usually isn't the right approach. Where's Dr. Fred M'bogo when you need him?

Cheers

Phil Hobbs

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It's a CMOS part. Maybe that spec is just a testing thing.

Yeah, no point in getting obsessed about electronics.

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Ah, OK, thanks. The jitter spec is a little scary--max 3.5 ps with an input of 300 mV at 400 MHz. That's 750 V/us, so the imputed voltage noise is

E_N = 3.5e-12*750e6 = 2.6 mV rms, i.e. about 84 nV/sqrt(Hz) assuming a 1 GHz bandwidth.

How does it do in real life?

Cheers

Phil Hobbs

The world has gone nutcase over low power with resultant "dog-slow" response. It's no problem at all to make a fast CMOS comparator... you just need to run at currents commensurate with driving the internal nodal capacitances.

I agree that an LVDS device can make a nice comparator... since I designed several of those Fairchild chips ;-)

The FIN1101 is a _repeater_, and there's nothing inherently there to create a large "offset", just a wide "transition" region I->O, with a differential output centered about a bandgap voltage. (I wonder if you could cascade two to get the gain up... probably.)

With limited CMR, you _could_ use a PECL device as a comparator, or use my venerable MC1650/51 (3.5ns, designed when I was ~25, and still sold by Lansdale :-), or the 10K/100K/ECLinPS descendents... if you can still find them. ...Jim Thompson

Yes, that was really my concern. A 1mA current should not damage the chip, since it is below the 50mA specified latchup current (or whatever). But that is no use if the facility is used as part of the normal operation of the circuit, and it goes nuts.

A simple example would be current limiting a 5V (or 24V) signal before feeding it to a 3.3V logic pin.

I have now stopped and thought about it. I still don't know why. What

And how does it improve on Larkins original totem pole idea (with the cap modification)? It looks like it would still be sensitive to noise around the switching point, if that was the original concern.

OK, thanks.

I have some single-supply opamp circuits where I want to measure (or integrate) a small negative current. So normally feedback keeps the summing junction at zero volts. But during startup there could be transients, or if the integrator saturates perhaps.

Bootstrapped Schottky diodes can help, if you can stand the Johnson noise from their zero-bias resistance. But it's best to test for latching mechanisms as well, just so you know what you're dealing with.

Cheers

Phil Hobbs