You can get rid of the static error by flipping it upside down and using the lock detector to control a FET switch.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Then there's that obscurely defined "lock detector" ;-) ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?
I don't have to actually define clever algorithms, I only need to be reasonably sure that one exists. I have smarter people to actually make it happen.
The trick would be, as you noted, to slow down the rate of slew of the edges, so we don't keep over-running the lock point. That means, get the frequency close somehow before closing the loop. That's pretty much the acquire/lock dilemma in all PLLs.
Applying a ton of FPGA logic helps.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
My PLLs usually need both phases, so doing a lock detector is pretty simple. It was left as an exercise for the student. ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Or else a PFD. ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I've not used that for lock detection, but I've used it for synchronous signal extraction (some 43 years ago):
...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?
We've done that in an FPGA, with up and down logic blips instead of a charge pump. Rob did some clever no-deadband algorithm, and I did the circuit.
But for picosecond time alignment, we prefer the ecl dflop thing. If nothing else, FPGAs have terrible delay tempcos. And it's fun to design with single gate and flop chips on boards, like in olden days.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Sure. I was merely proposing a PFD as an acquisition aid, if you happen to have the quadrature phase available, which I usually do.
Other sorts of lock detectors exist, of course.
Sure. I still use a fair amount of MSI in protos and really low-cost designs.
Cheers
Phil Hobbs
And of course a D-flop PD also works at 0 degrees, so a PFD acquisition aid is a natural fit.
Cheers
Phil Hobbs
All you've demo'd is a Schmitt. Show us the behavior with a typical input from a PD. Better yet, closed loop, full PLL. ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?
He *said* it was "left as an exercise for the student."
(That was of course a guess-who.)
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I've never simulated one of those, though I've built dozens--my first one was in 1982, at which point I thought I was the first to think of it. Turned out to have been invented a few years before.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I invented this
which I'm sure someone else did first.
What's cool is that, with suitable math inside the FPGA, the VCO frequency need not be the reference frequency. It's vaguely a sort of DDS PLL.
One minor annoyance is that the good fast ADCs have several clocks of pipeline delay, so the loop can't be super fast.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Looks like a good fit to the sorts of things you folks make--an extra ADC and a corner of a big FPGA is reasonable. If I needed something like that, I'd probably tend to use some sort of delta-sigma-ish loop with a 1:1 PLL on the output to clean up the spurs.
But my stuff doesn't have the timing constraints of yours, at least not so far. I'm starting a DARPA project to make an ultrastable polarimeter in a month or so, which is getting into the same sort of territory.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I guess one could use a PLL to clean up a DDS. But if you need not-very-agile CW, there are some shockingly good synthesizer chips around these days, with built-in VCOs.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
It does work. Introduces a phase offset, but probably OK for most analog loop applications.
I think I may have spotted a _tight_ lock indicator method (for PFD applications). I'll test and see. ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?
I just remembered... avoid the ramp jerk, insert current from Schmitt at juncture of feedback R and C. ...Jim Thompson
-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?
DDS spurs are a bit of a harder nut, because at some M and N values they're very close-in. In the 2-D heterodyne laser microscope I built a couple of years ago, I needed to take two octave-band VCO signals (f_x and f_y) and form 2(f_x + f_y) + 21.4 MHz. Doing the offset loop and mixing was OK, but the frequency doubler left a horrible mess--spurs everyplace, crisscrossing the whole band.
A 1:1 loop cleaned it up amazingly, which was fortunate. ;) I didn't need super low jitter for this job--for RF purposes the path difference was only a few hundred cycles due to the acoustic delays, and my measurement was pretty slow.
The good news is that it took only a week to build, which is a lot faster than I could have done it with DDSes + PLLs. (I did get an AD9956 dual DDS+PLL eval board, and would have used that chip for the final version. Unfortunately Intel pulled the funding at a very inconvenient moment.
Back before DDS and fancy fractional-N synthesis, the right answer would have been to choose some very high f_IF (500 MHz, say), use a PLL to offset f_x (say) by 21.4 MHz/2, mix up to f_x+510.7 and f_y+500, filter, mix to form f_x + f_y + 1010.7, filter, frequency-double, filter, mix with 2 GHz to get f_x + f_y + 21.4 MHz, and filter again. (All the high frequencies would have to be phase coherent as well of course.)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Using the 2N7002 trick pretty well fixes that.
I'd be interested in seeing it. I usually use a quadrature PD and a comparator. For PFDs, I nearly always use a window comparator on the loop filter output.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Nice, especially if transistors are free. Us board-level guys would just accept that you'd need a whole cycle of the ramp to lock up at the very edges, instead of only half a cycle. ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
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