Holy wasted opamps Batman.

OK thanks, I was just thinking about a low pass on the VCO input as the integrator. I'll have to think about that more. So the (inherent) time constant of the VCO is the frequency times some gain?

OK thanks again. I'm mostly an idiot about PLL's.

George H.

PLLs

One of my favourite tricks for handling that problem is to wrap a very weak positive feedback loop around the loop filter. When the loop is unlocked, K_phi drops to zero and the positive FB turns the loop filter into a slow t riangle wave oscillator. You have to make sure that df/dt

That's cute, scan for lock.

I've done adaptive loops, switching between a fast filter when unlocked, to a slow filter after lock. If you have an FPGA in the loop, you can do all sorts of tricks, like using frequency counters to get close to lock.

Interesting. Self-sweeping. I'll have to investigate that. ...Jim Thompson

Phil,

How does K_phi go to zero? Do you mean the _output_ of the phase detector goes high-Z? More explanation, please. ...Jim Thompson

That provokes this idea:

I'm not using the set or clear flop inputs. An FPGA could look at Q or Qbar and drive set and clear. It could do lock detection using some mumble-mumble algorithm, and take over and force (or PWM) the flop when the loop is out of lock.

An additional flop or two could do early/late detection and provide more info to the FPGA, but that's probably overkill.

It goes high-frequency.

K_phi is the short-time averaged PD sensitivity. If there's a beat note, it averages to zero.

Normal PD pull-in works by way of the beat note. Assuming the loop amp's ph ase isn't too large, on the ripple half cycle that tends towards lock, the beat frequency is less, so that half-cycle lasts a little longer, making a small DC component. Over many cycles, the loop amp integrates this till eve ntually the loop locks. Pull-in gets much weaker for larger beat frequencie s, which makes it vulnerable to offset voltages and such. There's also the phenomenon of false lock, where the loop amp's phase is too large, so the p ull-in signal goes to zero somewhere other than lock.

Cheers

Phil Hobbs

Well, since you generally need the quadrature phase for lock detection (and maybe AM demod), a PFD works well too. You can make it a weak perturbation like the positive FB, or else turn it off when the lock detector gives the OK.

The sneaky-sweeper idea works great for laser cavity-locking too, where you don't even have a beat note.

Cheers

Phil Hobbs

It does introduce a small amount of AM-PM conversion due to the resulting D C offset, which has to be a few times the worst-case offset of the PD and l oop amp. It wouldn't be rocket science to short the + input to ground when the lock detector says so.

Cheers

Phil Hobbs

We talk from different view-points. K_phi is the phase detector _constant_. K_v is the VCO _constant_. (See Gardner.)

How is this _physically_ implemented to get your sweeping method? ...Jim Thompson

t averages to zero.

'tain't constant though--it goes to zero far from lock.

I'm _quoting_ Gardner, from memory. See his discussion of pull-in.

Cheers

Phil Hobbs

The positive FB usually comes from a Schmitt trigger as in the usual tri/square oscillator, with the Schmitt's output coupled to the SJ via a big resistor. There are other things you can do, but that's about the simplest. You get a little big of a barb on the tri wave due to the resistor in series with the feedback cap.

See e.g. .

Cheers

Phil Hobbs

The problem with that is that it'll sweep way too fast. It isn't sufficient for the two frequencies to be the same--the phase has to be close enough.

Cheers

Phil Hobbs

OK. I see what you're up to. I'll have to experiment with that and see what error it introduces.

What I usually do, when I need fast acquisition (*), is widen the bandwidth temporarily.

(*) Rarely. I'm usually just doing synthesizers now-a-days... all my analog loop stuff was so last century >:-} ...Jim Thompson

The single-D _IS_ an early/late detector >:-} ...Jim Thompson

Since you have an FPGA, you could make a slow sweep by moving the set/clear edges. To it to lock reliably on the first pass, you need

df/dt

One might PWM the flop to get the frequency close, then turn it loose. Something like that.

We often use an FPGA pin, lowpass filtered, into a VCXO. We can wiggle it open-loop, PWM or delta-sigma, to trim the oscillator from a cal table entry when an external reference is not available. Then cut over to PLL mode when we have a reference.

Makes sense.

Cheers

Phil Hobbs