Holy wasted opamps Batman.

Hi George,

p9 in my Gardner, I must have different edition. Your circuit (c) has the advantage of clearly separating each element. Good for teaching? As shown circuit (b) has very high (open-loop) gain at DC so you can shunt R2+C with another resistor to set gain at DC - does what R2 does in your circuit (c).

Nothing to stop adding more parallel sections of R+C to set multiple breakpoints, a bit like RIAA phono preamps. You could even add some differentiation component with a C in series with R1.

So, yes. One lone op-amp can do an awful lot :)

piglet

I do (b) most of the time. An ordinary inverting amp lets you make nearly any rational function you like, as long as you're well beloq GBW.

Cheers

Phil Hobbs

I did (b) in my youth ;-)

Now I exclusively use charge pumps (a phrase I first coined ~1968). ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Why is it that the most unproductive members of our society blame the most productive members of our society for their failures?

Hey, I invented the infinite-gain D-flop phase detector when I was still in college. I've used it several time since, in super-low jitter systems. I still don't really understand it, but crude approximations and tweaking seem to work.

Is the gain _really_ infinite? Sorry! I couldn't resist >:-}

With 2 D-flops and 4 2-IN-NANDS you can make a very stable PFD. ...Jim Thompson

Of course you couldn't resist.

The setup/hold boundary on an EclipsPlus d-flop is unmeasurably narrow, femtoseconds. So an analysis of the loop may as well assume a zero time window on the phase detector, namely infinite PD gain.

So in a noiseless system, it becomes a bang-bang loop, and the phase detector output is PWM or sort of delta-sigma. But if you assume some jitter in the incoming data stream (the thing we lock to) and a slow loop filter, you can analyze it as as having a finite-gain slope, volts per picosecond. That seems to work. Well, it does work.

If you want picosecond time locking, any linear phase detector has too little gain. Millivolts or microvolts of DC error in or after (or even before) the phase detector wreck the timing budget. Temperature drift becomes lethal. That's where the d-flop phase detector is great: one EP51 flop with *infinite* gain. Metastability? That's our sign of success.

Do this...

in ECLips. ...Jim Thompson

Literally using single-ended signals into HC logic would have ghastly temperature errors. And any PD deadband or finite gain will be bad news.

One SO8 EP51 flop is sure a nice phase detector at 155 MHz. Delay tempco of ECL is a tiny fraction of CMOS. I have about 2000 "clients" (triggered devices) over a few acres of clean room that I'm triggering to picosecond precision.

Huh? The "single-ended signals" are logic levels.

I _said_ do it in ECLips.

...Jim Thompson

Yes. And any change in signal swing, or receiver threshold, or VCC, or temperature, translates directly into time shift. 0.1% threshold change on a 5 ns edge is 5 picoseconds. There are no logic levels; everything is analog.

Differential ECL is hard to beat for delay stability. Delay tempco is well under 1 ps/degC, and Vcc sensitivity is essentially nil.

Thanks, but the single d-flop works great. We do temperature compensate the overall product, with a cal factor, to get below 1 ps/degC overall, but we are compensating a lot more than the phase detector. The NIF timing modules are one of the few things that we temperature compensate, on each individual unit, at production test.

Thanks piglet, If it's inside a control loop I've never found it useful to roll off the DC gain of the integrator. I've tried it a few times, 'cause I'm thinking, "this thing has infinite gain at DC, scary", but inside the loop with some damping it's OK.

George H.

Can you post scribble so we can follow along? You're clocking a flip flop and integrating to get the time delay? (phase) George H.

Don't hold your breath ;-) ...Jim Thompson

one issue I have run into with the two op amp circuit...

during the time the loop is out of lock and trying to "acquire"

if the first amp can drive the second amps inputs to a voltage outside it's common mode range even briefly,

the op amp output may "invert" and the output will be wrong and the loop will "hang up" and never lock until the power is shut off and re-applied.

be sure to check, not just the expected range of voltages of normal operation but also the unexpected but possible range. I wish SW guys would follow that rule too.

Were you born with the double-dominant jerk gene?

I posted this in 2014:

(But Dropbox recently broke the old public link)

It's a complex version of the basic idea...

which has some interesting virtues. It's super simple. It has so much native gain, it doesn't need an integrator in the loop. In some cases it might not even need the RC filter. It will lock to ratio frequencies. It aligns the clock edges to picosecond accuracy and stability. In the NIF timing system, the ref clock is actually a Manchester-coded (biphase) data stream from a fiberoptic link; it's happy to lock to that, too.

With a differential ECL flop, it's wonderfully precise.

There's nothing wrong with infinite gain; it makes errors small. You just have to think about integrator windup.

But integration downstream of a bad phase detector doesn't help much.

Who's being the jerk? No one remembered your 2014 post and connected it to the context of this thread.

Try not to be such a bloviating asshole all the time. ...Jim Thompson

So, the answer to my question is "yes".

That's what I need. Thanks! (It's a beautiful mix of analog and digital. George like :^)

Isn't the R-R-C lag-lead thing(filter) an integrator?

Sure that makes sense. There's an integrator in the VCO too. (at least that's what Gardner says.)

It aligns the clock edges to picosecond accuracy and

Yeah, feed back is a wonderful thing. There's some time constant to the VCO though, isn't there? (how fast it can change.) Isn't one purpose of the PLL to clean up the input clock with that time constant?

I've never done a PLL, just reading and thinking about it. (On the DC end it's like other loops.)

I'm sloggin' through Gardner's noise chapter...can I assume the noise goes with the bandwidth?

George H. In the NIF timing system, the ref clock is actually a