Heatsinking electrically 'hot' nodes, SMD

Speaking of energy balances and negative thermal feedbacks, I've got an SMD board in a sealed box, in the sun, with a need to extract the heat out from inside as best one can.

Just plunking the board in a sealed metal can gives a 71oC rise, even for the very modest total dissipation (presently ~7W).

Obviously the thing needs heat-sinking. Regrettably, all the heat is generated at nodes that are electrically "hot," power nodes swinging

125W at ~280KHz. One square inch of the board in particular has to

dissipate about 3.5W.

I suppose I could insulate the bottom layer and take the heat out there, but I don't like capacitively coupling EMI to the case. I also don't like bringing two nodes that close that, connected, would break the device. I don't want its 'life' depending on a silpad or a mica washer either.

| || || | .--------------. .---------------. .-|--||--||--|-. | | | | | '--''--''--' | --. .---------------------. .----. | |= | | '----' | Q1 |= | | | | |.-------- |= | | .-----. || |= | | =| |= .-------. --' | | =| Q6 |= | | | | | | L1 | =| |= | |R4 | | --. | | =| |= '-------' |= | | '-----' || Q2 |= | | | | |'--------- |= | | | | | |= | | | | |

---' '---------------------' | | | | | | | | C1 C2 C3 | | .nnnn. | | .nnnn. .nnnn.| | .--..--..--. | '---| |-----' '-| |--| |' '-|--||--||--|-' .---| Q3 |---------| Q4 |--| Q5 |-..-|--||--||--|-. | | | | | | | || '--''--''--' | | 'uuuu' 'uuuu' 'uuuu' || | | || | | .----. .----. .----. || | | |----| |----| |----| || | '------| |--| |--| |-----'| | .------| R1 |--| R2 |--| R3 |------' | | |----| |----| |----| | | '----' '----' '----' | | | | GROUND | | |

I think I'm going to leave the hot stuff swinging hot on top, and use the five layers underneath as ground, with a ring of vias around the periphery to help move the heat from layer #2 to layer #6.

This way the heat only has to travel 0.010" in FR-4 (from top to layer #2), before getting a copper-assisted boost to the bottom (layer #6). 0.010" instead of 0.062" cuts the FR-4 path by a factor of five or so. The five Cu pours also create lots of spreading, which spreads the vertical thermal path through a much wider patch of the board. That helps too.

Net result should be ballpark 2-3oC/W top-to-bottom for this 1in^2 patch, which I can then safely tie thermally to the enclosure for another

Reply to
dagmargoodboat
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Seal the box, pull a vacuum inside and inject something like Flourinert to turn the entire enclosure into a heat pipe.

Reply to
Ralph Barone

That's not extreme.

If you want to use FR4 for electrical insulation, you might use multiple layers in parallel. Put "hot" pours on 1, 3, and 5, heavily via'd, and have ground on 2, 4, and 6.

Better yet, make 6 hot, as big a pour as possible, and heat sink it to the case, as noted below. 1, 3, 6 hot, 2, 4, 5 ground.

Bergquist, Chomerics, and Laird make thermal interface "gap pad" material, with optional adhesive. I've used it between the bottom of a PCB and the metal enclosure. The thermal conductivities are in the range of 1 to 5 W/m-K and the texture varies from foam to recently-used bubble gum. You can get it up to about 1/4 inch thick, but obviously thinner is better.

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you can see some lurking under that PCB. This one had to be silicone-free, so I used two layers of a Bergquist 1/8 thick material, which was available. My dissipation was, coincidentally, roughly 7 watts. There were several parts making hot spots, but the overall PCB temperature was fairly uniform; lots of copper.

The customer insisted on adding the two heat sinks. Their air dissipation is useless, but their baseplates do extract heat from the chip hot spots and spread it laterally, across the entire BGA package, which helps transport heat down into the PCB and eventually through the thermal pads to the box. That was hard to quantify.

Your PCB should of course spread the heat out over as wide an area as possible, lots of vias and lots of copper. Sounds like you're doing that.

I wound up doing a massive thermal study on this particular board/box, but it's not public. Email me, saying the appropriate things.

Reply to
John Larkin

Gee, that sounds like an awful lot of trouble and expense compared to good thermal layout. It adds a reliability problem too--if your scheme leaks, the unit dies.

Cheers, James Arthur

Reply to
dagmargoodboat

Though IBM did exactly that in the '80s. The problem wasn't leaks, rather the phase change causing any impurities (i.e. the "black plague") to be deposited on the chips. The solution was worse (for leaks). A piston rests on the back of the chip and the module filled with Helium to further lower the thermal resistance. They used a version of that packaging for a decade or two (still may, for all I know). The thermal design was for 1200W per module with a junction temperature of 85C (heating chips were used for "low power" modules to keep the Tj at 85C).

Reply to
krw

Just throwing it out there. It's worth exactly what you paid for it.

Reply to
Ralph Barone

It's quite modest really, but the temp. rise is, well, just what you'd expect.

I just want to use the FR4 between layers #1 and #2 for electrical insulation.

  1. - ---- hot X||XXXX
  2. -++---- GND X||XXXX
  3. -++--- hot DIAGRAM: Thermal feedthroughs join 2-6. No connection X||XXXX to layer 1.
  4. -++---- GND X||XXXX
  5. -++---- hot X||XXXX
  6. -++--- GND

I considered effectively paralleling FR4 thermally, as you're describing. That's pretty fun. But alternating electrically active and gnd layers would maximize the stray capacitance load on the active nodes, which I'm trying to avoid. Between that and the prospect of capacitively coupling EMI from the hot bottom nodes into the case, I don't think it's worth gaining that last 1C/W in this instance.

Hmm, scratches head...no, that's only 23nF stray for my geometry, if I did that right. Trivial, loading-wise. You're right, might be worth doing.

  1. -++- --- hot X||X||XXX
  2. -||-++--- GND X||X||XXX
  3. -++-||-- hot DIAGRAM: Thermal feedthroughs join 1,3,5, and X||X||XXX 2, 4, 6
  4. -||-++--- GND X||X||XXX
  5. -++-||--- hot X||X||XXX
  6. - -++-- GND

But if I keep all the current on layer #1, layers #2-6 can be ground pours and there's a considerable spreading advantage--ground pours can be much larger than the hot-spot area.

I'll have to do some figuring to see which is actually better. The top FR-4 is just 2oC/W by itself, which isn't awful.

'6' electrically and thermally hot works if I use an insulator to tap out the heat. There are four separate nodes needing heat-sinking, and they're at different electrical potentials. I'd much rather #6 = ground, though. Quieter & safer.

Thanks, that's handy.

Most kind, but I'd be uncomfortable--you earned it the hard way, and it's proprietary.

Cheers, James Arthur

Reply to
dagmargoodboat

IBM did some fancy stuff!

This simple critter has to live in the rough, so KISS^2 rules.

Cheers, James Arthur

Reply to
dagmargoodboat

Hey, no worries--it's a fun idea. In other situations that might be *the* thing to do.

Cheers, James Arthur

Reply to
dagmargoodboat

Production, too! It wasn't just in the lab.

Well, I didn't really expect him to use helium cooling. ;-)

Reply to
krw

23nF sounds high to me. 0.062 FR4 is 15 pF/sq inch. So 10 mil FR4 is about 100. 1 sq inch paralleled 5x is about 500 pF.
Reply to
John Larkin

I used 15x20mm, .25mm dielectric thickness, er=4.4, times 5. (That describes the swingin'est node.)

I'll have to check the calculation tomorrow--I wrote a spreadsheet gizmo so I might've goofed. It gave the right answer for a 1m^2 parallel plate cap in a vacuum, but that's all I tried. Could be a data entry error too.

A drawback of the parallel thing is that the 'hot' vias come out the bottom, so I'd need insulation.

I did some quick calculation of thermal via performance, which needs consideration too. I was too optimistic--the net 0 is non-trivial. Ever stuff dummy TH parts for solid copper fill? I might.

Cheers, James Arthur

Reply to
dagmargoodboat

So we invent a new component, a copper square with a bunch of pins poking out one side. It would look vaguely like a pin-fin heat sink with skinny pins. You solder it to the bottom (or maybe the top) of a PCB and the pins become mega filled thermal vias.

Reply to
John Larkin

Den mandag den 9. marts 2015 kl. 06.17.46 UTC+1 skrev John Larkin:

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-Lasse

Reply to
Lasse Langwadt Christensen

It needs multiple connection points. The major limit in PCB cooling is often the thermal spreading resistance of the copper, so cooling a single point often isn't enough. 1 Oz copper is, electrically, around

500 uohms per square and thermally, around 70 K/W per square.

Ordinary pads and spacers, pressed-in PEMS maybe, managed properly, would be about as good as that thing.

Reply to
John Larkin

Den mandag den 9. marts 2015 kl. 16.00.16 UTC+1 skrev John Larkin:

the point of those "thermal-connectors" is that go through the pcb and can being soldered directly to the thermal pad so you don't have to go through spreading resistance or fr4 first

-Lasse

Reply to
Lasse Langwadt Christensen

I like the video with the screen printing of thermal paste with a credit-card squeegee. I have never done it by hand. I either just hand solder each joint with a soldering iron and wire solder, or else have a proper $$$ stencil made and have it done by my assembly house. Could be worth trying for prototypes, I think some of the low cost prototype board makers sell low cost stencils too.

--

John Devereux
Reply to
John Devereux

Do you mean, like, solder a power-pad IC directly to the post? I guess that would work, but you might still need insulation.

My production people might lynch me if I asked them to reflow or rework that!

Reply to
John Larkin

Den mandag den 9. marts 2015 kl. 17.15.18 UTC+1 skrev John Larkin:

that's what they are made for,

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I've never tried them but the ideas seems ok, and I'm not sure production is that bad. can't much worse than IMS

-Lasse

-Lasse

Reply to
Lasse Langwadt Christensen

I think most protobard makers supply stencils too, the stencil/paste and hotplate/toasteroven seem to be a common diy process now.

I've used it, the only problem was a bit too much paste on the pads, I hadn't realized the assembly house usually tweak the data to reduce openings before ordering a stencil

-Lasse

Reply to
Lasse Langwadt Christensen

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