Hi,
I have several nodes in my design (registered nodes) which do not have a "driving" purpose. But for later use of SignalTap (Altera tool to make internal FPGA nodes visible) I do want the synthesizer not to optimize these nodes away. On the other hand I do not want to route these nodes to output pins because of a limited amount of available pins.
Is there some possibility to avoid that these registerd not used nodes are optimized away ?
Thank you for your suggestion.
Rgds André