SPICE help, please

Is it LIMPTS or the syntax? PIVTOL should be 1E-20, though that seems ridiculously small.

I don't understand the "X" problem?

You need to make it a file that ends in .cir, and all directives AND netlist must be contained in that file.

Some "Spice" variants may not accept ; at the beginning of a line, use

• instead.

Should work, I see no gross violations. What error messages do you get?

...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

No need to ditch the whole .option card, just delete the "LIMPTS" statement. Maybe this is similar to "plotwinsize, in LTSpice.

AFAIK, LTSpice does not honor .plot statements, *maybe it should*.

You need to run the netlist, then go into the plot pane, right click, and select visible traces.

If it won't work in TopSpice without the .LIMPTS, you can't

Make a symbol for your codatron subckt, draw the schematic, and include the subckt.

Or, alternatively, just run the existing netlist, like you already did.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

• The syntax is correct for TopSpice; LTspice complains, as i said.

• You know, when you need a widget that is not simple-minded; it is a sub-circuit call..

• That is EXACTLY what i have..the listing i gave is the contents of Codatron.CIR .

• For example LTspice??

• Read what i said..look at end here for more info.

A snip from output file: CODATRON EMULATION IN TESTING ARRAY

**** TEMPERATURE-ADJUSTED VALUES TEMPERATURE = 25.000 DEG C *********************************************************************** 0**** DIODE MODEL PARAMETERS 0NAME IS VJ CJO

DMOD1 7.350D-15 1.002D+00 0.000D+00 DMOD2 7.350D-15 1.002D+00 0.000D+00

0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0*ERROR*: MAXIMUM ENTRY IN THIS COLUMN AT STEP 12 (5.000000D-05) IS LESS THAN PIVTOL 0 SOURCE STEPPING METHOD FAILED Number of steps = 7 Power supplies at .781% 1*ERROR*: NO CONVERGENCE IN DC TRANSFER CURVES AT I1 = -2.000D-04 0LAST NODE VOLTAGES:

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

(101 ) .0000 (102 ) .0000 (103 ) .0000 (104 ) .0000 (105 ) .0000 (201 ) .0000 (202 ) .0000 (203 ) .0000 (204 ) .0000 (205 ) .0000 (98 ) .0000 (3.X0101 ) .0000 (3.X0102 ) .0000 (3.X0103 ) .0000 (3.X0104 ) .0000 (3.X0105 ) .0000 (3.X0201 ) .0000 (3.X0202 ) .0000 (3.X0203 ) .0000 (3.X0204 ) .0000 (3.X0205 ) .0000 (3.X0301 ) .0000 (3.X0302 ) .0000 (3.X0303 ) .0000 (3.X0304 ) .0000 (3.X0305 ) .0000 (3.X0401 ) .0000 (3.X0402 ) .0000 (3.X0403 ) .0000 (3.X0404 ) .0000 (3.X0405 ) .0000 (3.X0501 ) .0000 (3.X0502 ) .0000 (3.X0503 ) .0000 (3.X0504 ) .0000 (3.X0505 ) .0000

0 ***** JOB ABORTED

TOTAL JOB TIME .05

• "run the netlist" ?? in LTspice, how? There are NO visible traces (yet).

• In LT spice, how is this done (fake a symbol), and how does one refer to the subcircuit,as there seems to be no X..

Well if i did that, then why do i get nothing?

Maybe you got snagged by LTspice's "diode" ;-)

Set all options back to default, and try it again. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

ESTO ?:-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

Because, as I said, LTSPice does not honor .plot statements directly in netlists.

A blank plot window should have automatically opened, however. Go into that window (click on its title bar). Left click, or alternatively select "Plot Settings", then "Visible Traces". You'll be offered V(101), V(103), V(201), V(203). For a start, select V(203). A plot will appear of V(203). Right click on the "V(203)" header, an edit box will appear. Edit "V(203)2 to read (V203,103). Click OK, the plot will then change itself. Do the same for the rest. You can then save those plot settings.

LTSpice is GUI-oriented. You're expected to probe the circuit voltages and currents directly from a schematic. From someone else's netlist, it's a PITA. IMO, it should support .plot and .print statements, however. Polar and Smith plots would be nice, too. Even Berkeley Spice 3 could do those. The .net directive is probably the most useful LTSpice innovation to me, Zin, Zout, Yin, Yout, s-parameters, h-parameters, automatically.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

LTspice follows the PSpice approach...

.PROBE [V(Node) List]

or wild card...

.PROBE V(*) I(*) W(*) D(*) NOISE(*)

You still have to pick from a list ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

I should have also mentioned...

.PRINT [V(Node) List]

Puts the data in the .OUT file as a numeric list.

I do that all the time in PSpice to get numeric data into Excel, etc. In PSpice you have to use a symbol to force that .PRINT statement, PSpice has removed it from the "directives" list. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

LTSpice runs it, albeit slowly, if you lose the LIMPTS. The PIVTOL is OK.

NOOPITER makes it a little faster.

I'm not surprised it's slow with all those 10E20 resistors!

It gives plots that you would expect from looking at what's in there.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

That error listing is from TopSpice.. In any case,after a LOT of time spent learning how to make a new part, i have something "working". Will post separately.

What does "ESTO" supposed to mean? 1) "ESTO en Línea", 2) "Esto Photographics", 3) "Educational Seminar for Tourism Organizations", 4) "Earth Science Technology Office", 5) "Esto, Florida", 6) "European Science and Technology Observatory", 7) "Idaho State Motto Esto Perpetua It Is Perpetual" OR WHAT??

Oh, i got a blank plot window..totally useless as i cannot probe a non-existent schematic.

• What i did, was spend a lot of time learning how to make a new part; then i redrew; results in a new post.

Hmm..did not know about .PROBE; pita that .PRINT and/or .PLOT does not work.

See my separate posting.

Just ignores .print.

No .OUT file, just .RAW, which is node data in binary, unless ASCII is specified in Control Panel. The rawfile is generated automatically, in all cases.

There is a facility to export waveform data as ASCII text files. The one generated by Robert's netlist comes to some 33MB.

I suspect Robert's DOS Spice is running out of memory before it can complete.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

AFAICS, LTSpice just ignores PSpice-type .probe statements. I've never gotten any response to them.

Nothing in the manual to suggest otherwise.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

You don't need a schematic.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

Much apologies for the length; this allows anyone else to run and test. Questions are at the end.

Here is the LTspice listing, then the .PLT and the corresponding .ASY:

** Array5X5.asc Version 4 SHEET 1 1076 808 WIRE 96 -208 -16 -208 WIRE 192 -208 96 -208 WIRE 288 -208 192 -208 WIRE 384 -208 288 -208 WIRE 512 -208 384 -208 WIRE 512 -176 512 -208 WIRE -96 -32 -256 -32 WIRE 32 -32 -96 -32 WIRE 128 -32 32 -32 WIRE 224 -32 128 -32 WIRE 320 -32 224 -32 WIRE 416 -32 320 -32 WIRE -16 32 -16 -128 WIRE -16 32 -96 32 WIRE 96 32 96 -128 WIRE 96 32 32 32 WIRE 192 32 192 -128 WIRE 192 32 128 32 WIRE 288 32 288 -128 WIRE 288 32 224 32 WIRE 384 32 384 -128 WIRE 384 32 320 32 WIRE -96 64 -96 32 WIRE 32 64 32 32 WIRE 128 64 128 32 WIRE 224 64 224 32 WIRE 320 64 320 32 WIRE -336 80 -336 -32 WIRE -96 80 -256 80 WIRE 32 80 -96 80 WIRE 144 80 32 80 WIRE 224 80 144 80 WIRE 320 80 224 80 WIRE 416 80 320 80 WIRE -96 96 -96 80 WIRE 32 96 32 80 WIRE 144 96 144 80 WIRE 224 96 224 80 WIRE 320 96 320 80 WIRE -16 144 -16 32 WIRE -16 144 -96 144 WIRE 96 144 96 32 WIRE 96 144 32 144 WIRE 192 144 192 32 WIRE 192 144 144 144 WIRE 288 144 288 32 WIRE 288 144 224 144 WIRE 384 144 384 32 WIRE 384 144 320 144 WIRE -336 176 -336 80 WIRE -112 176 -256 176 WIRE 16 176 -112 176 WIRE 128 176 16 176 WIRE 208 176 128 176 WIRE 304 176 208 176 WIRE 416 176 304 176 WIRE 688 176 416 176 WIRE -96 192 -96 144 WIRE 32 192 32 144 WIRE 144 192 144 144 WIRE 224 192 224 144 WIRE 320 192 320 144 WIRE -112 208 -112 176 WIRE 16 208 16 176 WIRE 128 208 128 176 WIRE 208 208 208 176 WIRE 304 208 304 176 WIRE -16 240 -16 144 WIRE -16 240 -112 240 WIRE 96 240 96 144 WIRE 96 240 16 240 WIRE 192 240 192 144 WIRE 192 240 128 240 WIRE 288 240 288 144 WIRE 288 240 208 240 WIRE 384 240 384 144 WIRE 384 240 304 240 WIRE -336 272 -336 176 WIRE -80 272 -256 272 WIRE 32 272 -80 272 WIRE 112 272 32 272 WIRE 224 272 112 272 WIRE 320 272 224 272 WIRE 416 272 320 272 WIRE 688 272 688 176 WIRE -80 288 -80 272 WIRE 32 288 32 272 WIRE 112 288 112 272 WIRE 224 288 224 272 WIRE 320 288 320 272 WIRE -112 304 -112 240 WIRE 16 304 16 240 WIRE 128 304 128 240 WIRE 208 304 208 240 WIRE 304 304 304 240 WIRE -16 336 -16 240 WIRE -16 336 -80 336 WIRE 96 336 96 240 WIRE 96 336 32 336 WIRE 192 336 192 240 WIRE 192 336 112 336 WIRE 288 336 288 240 WIRE 288 336 224 336 WIRE 384 336 384 240 WIRE 384 336 320 336 WIRE -80 384 -80 336 WIRE 32 384 32 336 WIRE 112 384 112 336 WIRE 224 384 224 336 WIRE 320 384 320 336 WIRE -336 400 -336 272 WIRE -96 400 -256 400 WIRE 32 400 -96 400 WIRE 128 400 32 400 WIRE 224 400 128 400 WIRE 320 400 224 400 WIRE 416 400 320 400 WIRE 688 432 688 352 WIRE 688 432 560 432 WIRE 736 432 688 432 WIRE 560 448 560 432 WIRE -16 464 -16 336 WIRE -16 464 -96 464 WIRE 96 464 96 336 WIRE 96 464 32 464 WIRE 192 464 192 336 WIRE 192 464 128 464 WIRE 288 464 288 336 WIRE 288 464 224 464 WIRE 384 464 384 336 WIRE 384 464 320 464 WIRE -336 496 -336 400 WIRE -96 496 -96 464 WIRE 32 496 32 464 WIRE 128 496 128 464 WIRE 224 496 224 464 WIRE 320 496 320 464 WIRE 688 528 688 432 WIRE 192 608 192 464 WIRE 448 608 192 608 WIRE 560 608 560 528 WIRE 560 608 528 608 WIRE 688 608 560 608 WIRE -16 688 -16 464 WIRE 96 688 96 464 WIRE 192 688 192 608 WIRE 288 688 288 464 WIRE 384 688 384 464 WIRE 560 688 560 608 FLAG -336 496 0 FLAG 512 -176 0 FLAG 416 80 202 FLAG 416 176 203 FLAG 416 272 204 FLAG 416 400 205 FLAG 96 688 102 FLAG 288 688 104 FLAG 384 688 105 FLAG 192 688 103 FLAG 560 688 0 FLAG -16 688 101 FLAG 416 -32 201 FLAG 736 432 FRC SYMBOL res -240 64 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R202 SYMATTR Value 10E20 SYMBOL res -240 160 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R203 SYMATTR Value 10E20 SYMBOL res -240 256 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName E204 SYMATTR Value 10E20 SYMBOL res -240 384 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R205 SYMATTR Value 10E20 SYMBOL res 80 -224 R0 SYMATTR InstName R102 SYMATTR Value 10E20 SYMBOL res 272 -224 R0 SYMATTR InstName R104 SYMATTR Value 10E20 SYMBOL res 368 -224 R0 SYMATTR InstName R105 SYMATTR Value 10E20 SYMBOL res 672 256 R0 SYMATTR InstName R99 SYMATTR Value 20K SYMBOL res -240 -48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R201 SYMATTR Value 10E20 SYMBOL res -32 -224 R0 SYMATTR InstName R101 SYMATTR Value 10E20 SYMBOL current 688 528 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I1 SYMATTR Value 0 SYMBOL res 544 432 R0 SYMATTR InstName R98 SYMATTR Value 10E20 SYMBOL res 176 -224 R0 SYMATTR InstName R103 SYMATTR Value 10E20 SYMBOL res 544 592 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R97 SYMATTR Value 1 SYMBOL Codatron -112 16 R0 SYMATTR InstName U0101 SYMBOL Codatron 16 16 R0 SYMATTR InstName U0102 SYMBOL Codatron 112 16 R0 SYMATTR InstName U0103 SYMBOL Codatron 208 16 R0 SYMATTR InstName U0104 SYMBOL Codatron 304 16 R0 SYMATTR InstName U0105 SYMBOL Codatron -112 144 R0 SYMATTR InstName U0201 SYMBOL Codatron 16 144 R0 SYMATTR InstName U0202 SYMBOL Codatron 128 144 R0 SYMATTR InstName U0203 SYMBOL Codatron 208 144 R0 SYMATTR InstName U0204 SYMBOL Codatron 304 144 R0 WINDOW 3 22 -20 Right 2 SYMATTR InstName U0205 SYMBOL Codatron -128 256 R0 SYMATTR InstName U0301 SYMBOL Codatron 0 256 R0 SYMATTR InstName U0302 SYMBOL Codatron 112 256 R0 SYMATTR InstName U0303 SYMBOL Codatron 192 256 R0 SYMATTR InstName U0304 SYMBOL Codatron 288 256 R0 SYMATTR InstName U0305 SYMBOL Codatron -96 336 R0 SYMATTR InstName U0401 SYMBOL Codatron 16 336 R0 SYMATTR InstName U0402 SYMBOL Codatron 96 336 R0 SYMATTR InstName U0403 SYMBOL Codatron 208 336 R0 SYMATTR InstName U0404 SYMBOL Codatron 304 336 R0 SYMATTR InstName U0405 SYMBOL Codatron -112 448 R0 SYMATTR InstName U0501 SYMBOL Codatron 16 448 R0 SYMATTR InstName U0502 SYMBOL Codatron 112 448 R0 SYMATTR InstName U0503 SYMBOL Codatron 208 448 R0 SYMATTR InstName U0504 SYMBOL Codatron 304 448 R0 SYMATTR InstName U0505 TEXT -192 792 Left 2 !.dc I1 0 20u 0.001u TEXT 32 784 Left 2 !.option noopiter TEXT 640 -152 Left 2 !.MODEL DMOD1 D (BV=398)\n.MODEL DMOD2 D (BV=3840)\n.SUBCKT Codatron 1 2 ; HT-400\n DZ1 1 3 DMOD1\n DZ2 2 3 DMOD2\n.ENDS Codatron ** Array5X5.plt [DC transfer characteristic] { Npanes: 1 { traces: 3 {524290,0,"V(203)"} {524291,0,"V(201,103)"} {524292,0,"V(201,101)"} X: ('µ',0,-2e-005,4e-006,2e-005) Y[0]: ('K',1,-400,400,4000) Y[1]: ('µ',0,1e+308,4e-006,-1e+308) Volts: ('K',0,0,2,-400,400,4000) Log: 0 0 0 GridStyle: 1 } } ** Codatron.asy Version 4 SymbolType CELL LINE Normal 36 -28 44 -36 LINE Normal 16 -48 36 -28 LINE Normal 16 -48 44 -36 LINE Normal 31 28 16 48 LINE Normal 16 48 41 43 LINE Normal 58 -16 40 -32 LINE Normal 58 -16 58 -16 LINE Normal 58 21 58 -16 LINE Normal 58 21 58 21 LINE Normal 31 28 41 43 LINE Normal 58 22 16 48 LINE Normal 58 16 58 22 WINDOW 0 24 16 Right 2 WINDOW 3 24 -20 Right 2 SYMATTR Value Codatron SYMATTR Prefix X SYMATTR Description Bipolar NPN transistor, open base PIN 16 -48 NONE 0 PINATTR PinName Anode PINATTR SpiceOrder 1 PIN 16 48 NONE 0 PINATTR PinName Cathode PINATTR SpiceOrder 2 ********** QUESTIONS: 1) Note V(201,103) which represents all parts "on a line", the same horizontal or vertical driven line, breaks down; what is the current path? and why? Can that be prevented? 2) Note V(201,101) which represents all parts "off the line",meaning not on any (directly) driven line; it looks exactly as if the (simulated) E-B is forward biased and the (simulated) B-C is breaking down; again, what is the current path? and why? Can that be prevented?

Reason for all of this fuss.. I need to test a LOT of units in minimum time, and had the idea to put them in an array as seen, thus minimizing number of wires from oven to outside world where the H and V lines would be in another array that ties to test connectors (say BNCs).