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I am pretty sure that is bass-ackwards (read reliable and glitch free only with synchronous counters). Ripple counters have always been noted for the long times to reach correct value. Don't trust me, jig it up and find out for sure.
Think about the states.
John
Yep. Ripple counters are the fastest counters in FPGAs too. That carry-look-ahead and carry-save stuff is for college kids. ;-)
Think about the states.
John
On Sep 2, 8:49=A0pm, John Larkin wrote: [....]
I assume this is about:
Q2 Q1 AND
0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0So long as the prop-delay through a ripple counter is less than a half cycle, you can AND decode a pulse from them at the full count case.
For more condition decoding, the Johnson counter is the way to go for easy decoding. It needs N/2 flip-flops instead of log2(N).
A handy trick when making a largish counter is to use 2 bit Johnson counters for pairs of bits. It often works out to need less hardware to do.
Right. The AND decode is glitch-free for all codes up to the desired one, assuming all the flops settle before the next clock. A synchronous counter generally won't guarantee that.
Ripple counters usually have the highest Fmax in any given technology. Synchronous counters settle fastest. Sometimes a hybrid works best, a ripple flop or two ahead of a synchronous counter.
A pseudorandom sequencer can make an interesting divider if you don't mind the clock fanout and the goofy terminal state decode. Some microprocessors have been built that used pseudorandom shift registers as their program counters; must be interesting to program.
John
Why is why you decode synchronous counters synchronously.
Johnson counters are generally faster. Johnson counters are usually used in prescalers.
Johnson counter ahead of a synchronous counter.
Yep, one of the first IBM microprocessors had a LFSR as the program "counter". Programming wasn't a problem at all. That's what they make assemblers for. ;-)
I know that one of the micros that was in video games had a timer based on a pseudo random generator. You could program any delay you wanted by picking a number out of a table and plugging it into your source come. A pseudo random program counter sounds perhaps a little easier to deal with. The assembler just needs to do the same steps as it figures out where to put the bytes.
For a long time I have been suggested that program counters should decrement to help with top down software design, but that is another matter.
One convention is to refer to higher addresses as "down", ie, down in the program listing.
Maybe I should use a phantastron. You can get a 10:1 division with one tube.
John
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Take your own advice.
Or jig it up and test it.
I dare you.
--=20 Transmitted with recycled bits. Damnly my frank, I don't give a dear
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=46unny, that is usually exactly what a synchronous counter does guarantee, along with glitch free decoding. Of course the extra logic to do that does make them slower.
Yep. They make great binary, power of 2 dividers. However there is some clock skew between input and output. If the speed and division ratio are large enough you can have full or even multiple cycle offsets from input to output.
Jig it up and test it.
I thought that was the 'Deckatron'.
-- You can\'t have a sense of humor, if you have no sense!
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fI usually just think of them as "later" and hence down the list like you would with later dates.
Because the 8051 has a DJNZ instruction, the things like "for loops" usually end up with a variable decrementing. This can mean that the cells of an array are used in decreasing order etc. Having a PC that decrements wouldn't require as much rethinking.
With a blocking oscillator, you can do about as many.
Wake up. MooseFet already did it.
And I have tested it, many times.
Think about it: a given bit only ever rises *after* all the lesser-significant bits fall.
John
The Dekatron was an expensive complex decade divider gas-filled toob with built-in display.
I still have one!
ftp://jjlarkin.lmi.net/4FP7.jpg
The first thing I designed for money (80 cents per hour) was a radiation counter with 4 or 5 Dekatrons.
There was also a similar-looking vacuum tube that used a complicated magnetic field effect. No readout, expensive, but much faster.
A phantastron was a single pentode circuit that used a weird non-inverting gain mode to make a relaxation oscillator or a one-shot, usable as a frequency divider if you were careful. I think the old Tek timebase calibrator boxes used them.
John
An AND gate, decoding a count state of a synchronous counter, can and often does have decode glitches. That's because all of the comparator inputs transition simultaneously. So the comparator output must be used synchronously to be safe. Or hang a cap on the output!
A ripple counter AND comparator has no glitches below the programmed state, provided all the flops settle before the next clock. So it can be used as a DC clear into the counter. That's all.
John
I built my first 'scope, age about 16, using a 6AM6 as a screen coupled phantastron as timebase.
--
"Electricity is of two kinds, positive and negative. The difference
is, I presume, that one comes a little more expensive, but is more
durable; the other is a cheaper thing, but the moths get into it."
(Stephen Leacock)
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Perhaps, but the glitches in decoding ripple counters are well documented. And there are counters that count in very different ways, like ring counters.
Just the same, jig up a slow ripple counter and put that into a fast DAC and examine the output. See if that waveform is a clean monotonic.
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Take any nice (kind of slow just to make the point) ripple counter, feed it to a fast DAC and capture the waveform and post it. It gets really fun if you push the clock on the ripple counter. Oh and everybody else that has the capacity to do this is welcome to post waveforms and schematics.
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n tThat is quite a different matter than only using AND decoding. The decode with an AND gate only gets into trouble when the delay from the lower bit used to the highest gets up to half a cycle. Below that there are no glitches on the AND decoded output.
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