Using a PIC for a 10MHz divide-by-n counter?

Question

I need a 50% d.c divide-by-n counter running at a fixed input, providing

10MHz/n, n=1..2^21. I was hoping to find a HC logic chip that does this, but cant seem to find any. The 292/294 need n >= 4. The 4059 dos\\esnt seem to give a 50% dc. Is there any other chip that would work?

Another idea I had: suppose I use a 18Fxxx with a 10MHz Xtal, giving a Tosc of

40MHz. Clock=10Mhz. I can use the PWM module with the 10bit dc reg loaded with

The PR2 reg is set to 0. Looking at the block diagram this shd generate a HIGH PWM o/p every clock (0.1us). Every 1/2 clock (ie Tosc *

2) the PWM output would go low. This would generate a 10MHz 50% duty cycle pulse train. The datasheet doesnt say anything abt the max PWM freq, so Im not 100% sure of this. If this works, then I dont need any fancy CPLD. Of course theres still the problem of the low frequency end since the counter is 8 bits while I need around
21 bits, but Im thinking that shouldnt be too much of a problem to handle in software.

Thanks in advance

vkj

Frank Buss · Accepted Answer

There was a thread two months ago with lots of good ideas and solutions:

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You can try it in the MPLAP simulator. But a 18Fxxx PIC is more expensive than a small Xilinx CPLD.

Another disadvantage of this solution compared to a CPLD is more jitter, if you divide in software and don't do very careful opcode cycle counting.

stickyfox · Answer

Why don't you just use 21 bits of ripple counting and put a latch on the outputs? Set the increment to the rising edge of your crystal signal and the latch on the falling edge. You will get as close to 50% as your clock possibly can.

If you want to do the same in software, just set a counter to increment and use an interrupt to get the last few bits, but I'd just use discrete logic for something like this.

Actually I'd use a CPLD but that's assum> vkj wrote:

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Using a PIC for a 10MHz divide-by-n counter?

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