super fast divide-by-N

Once you have divided by 2 or 4, you are in the realm of fast logic (look at the various fast logic families).

One search I would suggest is 'fast prescalers'.

Jim has set you on the right path :)

Cheers

PeteS

Above, you imply that there are only 32 values of N (1-32). Can you multiply by 1/N instead?

That's a pretty broad range, Thomas. Like me asking a bank for a loan of $1,250 and saying I'll settle for a dollar.

Jerry

Hello,

I am looking for a fast divide-by-N chip with a high bandwidth. I'm hoping for an input frequency of 1 GHz but would probably settle for one around 80 MHz. Duty cycle doesn't matter for the DSP application I have in mind but I do need to run at 3V.

Thanks to anyone who knows of one and cares to share,

Thomas

It's a good approach, and the reasoning seems sound, but I was struck by the very large spread between "need" and "want".

Jerry

There are DDS's that can run off of a 1 GHz clock. The Analog Devices AD 9858, I think it is. That might be massive overkill for what you are doing.

Instead, you could divide the 1 GHz down by 4 or 8 using some kind of prescaler, and then feed the resulting 250 MHz clock to a CPLD or something which could implement whatever kind of divide-downs you want, and produce multiple copies.

You don't say anything about jitter.

I dropped comp.dsp, because it seemed to have more to do with hardware design.

--Mac

Thanks Jim,

Nice parts but I can only see a divided by 2 and divided by 4 from that company. I'm kind of looking for a divide by N. Maybe up to 32 or so.

Thanks, Thomas

Ah...yes?... I don't quite know what you mean here. I can see how they are equal mathematically, but I don't know how to achieve this with electronics.

Ha. Let me give you a bit of back ground then. I am really pushed for space. I need different clock frequencies thru-out my board. My highest frequency is a Fox RFXO running around a GHz. I would like to derive all other clocks from this one if possible. Next lowest frequency is around 80 MHz. Then a few after that. I hate PLLs and I don't want a bunch a xtals on my board. So I thought I would just divide down from my highest frequency. One chip solution would be the best.

Thomas

The important number is what is the minimum divide ratio that you need. If the minimum N is a reasonably large number then you can use the conventional approach used in RF synthesisers, where you have a fast prescaler (e.g. divide by 8 or 9) and then a slower block of logic that decides when to switch the prescaler into divide by 8, and when to use divide by 9.

You might be able to find a RF synth chip where the divider output is available at a pin. Look at the Analog Devices ADF4111 for example which can mux out the divider output to a pin.

Chris

Have you looked at ICS . You might find this useful or not

Upto 2GHz input and various divide outputs 1,2,4,8,16

They also do other dividers and buffers. Usually I find the costs, very low in small quantities. However distributing all the clocks divided around the board will be fun. ICS also do small PLL chips that work well and are cheap, small and could run off of one lower clock drive. Unless of course you all the clocks synchronised to the highest frequency.

I think he is talking about dividing a clock signal down by N, down dividing a digital value by N (e.g. in a DSP). I missed that point the first time too--reading this in a DSP group, I assumed it was a DSP question, but notice the cross-posts. It wasn't until I read some of the responses that I realized what he was trying to do.

Look at OnSemi, under high performance counters, you'll find ones that go 1.4GHz. You will pay for this performance :) If a few hundred Mhz is OK, then look at any modern 32 macrocell CPLD [ Xilinx / Lattice ], and they are closer to $1

-jg

MC100EP016A :

Rene

While a divide-by-N could be implemented with an up-counter and using some gating to detect N and asynchronously reset the counter, this will usually have some timing glitches. Usually a divide-by-N is implemeted with a presettable down counter, when "0000" is detected, N is loaded into the counter.

If you do not need the divide by 1, some synchronous presetting could be used, i.e. the gating detects the "0001" state and let the next clock pulse do the actual presetting.

This could be done with up-counters, but now the gating would have to detect the N-1 condition to perform a synchronous reset at the next clock pulse.

Paul

Thomas Magma skrev:

I'd think that whenif you find something that will divide 1GHz to

-Lasse

How about using the carry as synchroneous load ?

Rene

Lasse,

Nice to hear from you again! I think the OP might want a coherent division. Maybe not.

Jerry