1. Home
  2. Electronics Design
  3. divide-by-N
  4. Page 4

divide-by-N

ree

en

f

I am using a very low cost system so I'll post the two bit version based on the counter decode I showed earlier in this thread:

Q2 Q1 AND

0 0 0 *............ 0 1 0 ....*........ 0 1 0 ....*........ 0 1 0 ....*........ 0 0 0 ....*........ 0 0 0 *............ 1 0 0 ........*.... 1 1 1 ............* 1 1 1 ............* 1 1 1 ............* 1 0 0 ....*........ 0 0 0 *............

Notice how we get only downward glitches and never upward ones. This means that we can use this to ramp a voltage up to where a comparator trips to make a very nasty sort of ADC without the comparator tripping early due to glitches.

Reply to
MooseFET
Loading thread data ...

In Don Lancaster's TTL Cookbook, he mentioned a deglitcher that consists of a bank of D FFs clocked on the opposite edge from the counter flops.

The idea was specifically to get around the innate glitches in ripple counter decoding.

Admittedly, if you've got some 10 nS FFs, and are using 100 fS AND gates, you could still get a little glitch here and there.

Also, if all you need to decode is some ultimate state (like a "wrap now" or some such), then ripple counters can be coaxed into behaving sanely.

Cheers! Rich

Reply to
Rich Grise

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.