I need a divide by N chip, covering a divide range of 20 to 300 or so. I know I can build it with a binary counter and an 8 input nand gate. But, I'd like to have it all in one chip if possible.
They used to make these things for phase locked loop building blocks, but I don't see anything like that listed in the Mouser catalog...so I need some suggested vendors and part numbers that might be appropriate.
It would be nice if it had a crystal oscillator built in or perhaps just a crystal input. But, a plain ole divider would meet my needs and I could do my own oscillator.
If it covers a larger range of N values, that's ok too.
Has FPGA technology progressed to the point of being available to average users or is it still megabucks commercial users in big quantity technology?
If I could do the whole job with a single FPGA, I'd go for it in a heart beat.
My entire project involves a programmable binary divider, with programming being done by outboard switches to gate the desired combination of outputs back to the reset on the counter so that free running divide by N from 2 to 255 is all that's needed, with a 20 Mhz input to divide by N.
Any possibility of using a single fpga chip without breaking the bank???
Your requirements seem to be pretty modest. A CPLD would likely do the job for a few bucks. The Xilinx CoolRunner XCR3032XL-10CS48 is $2.15 in onesies.
They're the same, but different. ;-). CPLDs have fewer, but more complicated, programmable blocks. Basically they have a fairly large PLA in front of fewer latches. FPGAs are richer in latches and less rich in logic. To put it another way, FPGAs are finer grained programmable devices than CPLDs. The Xilinx cool-runner parts are flash based so don't need any external programmin. Their FPGAs are SRAM based and thus volitile.
You only need a few dozen latches (at most), so either would likely work. Non-volitile is likely a benefit for your application too.
THere are schematic capture tools, as well as "programming" languages (Verilog, VHDL, etc.). Personally, I'd rather use VHDL for such a project. It's easy to pick up for a small application like this. You could even do structural VHDL and instantiate the registers and logic directly. IMO, this is a perfect sort of application to get one's "feet wet".
Dunno. I haven't looked lately. Check the Xilinx site. The programming cable isn't all that expensive. Software for all but the largest devices is free. The third party software has more function but does get quite pricey (I had >$80K in Synplicity software on my laptop at one point).
Try opencores.com or do a search on "programamable logic", or some such. For my first design I had a really good introductory VHDL book. I can't remember the name off-hand, but I'll try to look it up when I get into work (my copy grew legs). I could probably whip together a VHDL "design" for what you want in a half hour or so. I'd have to re-read your requirements though. ...and it is Sunday. ;-)
Comp.arch.fpga is where all the Xilinx people hang out. They are quite responsive to their customers (and kind to newbs ;).
There is a reason Xilinx, Altera, et.al. are in business. Watch "feature creep" though. ;-)
Divid by N is trivial. How much similar junk/glue logic do you have that can be moved into a CPLD/FPGA.
Xilinx and Altera are the major players in the FPGA market. Both offer free software. Poke around on their web sites.
FPGAs seem to come in 2 flavors. One is the high performance, high price, bleeding edge. The other is high volume, low price, reasonable performanace.
At the low/simple end, you probably want a CPLD rather than a FPGA.
I'm more familiar with Xilinx's products. They make both FPGAs and CPLDs. Their on-line store says under $2 for CPLDs and ~$10 for FPGAs.
With Xilinx, their low cost parts are Spartan-3 for FPGAs and Coolrunner-II for CPLDs.
Beware. Newer chips won't support older 5V IO signals.
Most FPGAs need to be reprogrammed at power up. In a stand-alone system, that usually means you also need a serial PROM which may cost as much as the FPGA. If you have a CPU handy, you can load it with a few GPIO pins.
CPLDs also need to be programmed, but generally only once. With modern packages which have tiny pins you don't want to use sockets and a stand-alone programmer. Usually, you can program them via JTAG, usually a 6 pin connector and a programmer that plugs into the printer port.
The Xilinx Spartan-3 starter kit is $100. It's actually made by Digilent -
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If you are interested in FPGAs, that's a pretty good deal.
Their Coolrunner-II board is $50. I haven't used it.
They also offer an inexpensive programming cable for $12.
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It's included in the Spartan-3 kit and I assume that's what is included in the Coolrunnter kit.
If you haven't used FPGAs or CPLDs before, getting one of the starter kits is probably a good idea. Digilent has lots of documentation on the web, including schematics.
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Thanks Keith, I appreciate the intro to this technology.
I need a 15 Mhz input frequency with divide by 2 to 512 capability selectable from front panel switches. It has to be TTL level output.
I don't need (nor want) any complicated frequency counter, frequency display or a any BCD select switches to read out the frequency directly. I don't need (nor want) a shaft encoder to change the divide by N value or anything like that.
It is for a local oscillator for a quadrature based zero IF receiver which is why I don't want a DDS or a PLL solution.
Just a line of binary switches (simple DIP switches is the full extent of the hardware) I want......nothing fancy.
The only 'frill' I might like is a second custom divider chain to give
100 Hhz, 25 Khz and 10 Khz switchable calibration markers, similar to the types used in 60/70's vintage receivers before the days of accurate frequency counters. But, that's secondary.
Here's the deal.....
I can't use the 14 stage cmos ripple counter, it is missing some of the outputs, so I have to use a specialty crystal oscillator that has a prescaler built in and a 7 stage binary counter (cmos).
So, that's 2 chips (so far). Next I have to add pull ups and switches to control the prescaler in the oscillator and to select which binary outputs to gate together to reset the counter as needed to produce the desired output frequency.
A third chip (8 input AND gate) is needed just to gate the desired binary counter outputs together, so now I'm up to 3 chips.
If I can do it all in a single CPLD, that would be much easier, especially with fabrication. The size of the CPLD circuit would probably be much smaller also.
The pull ups and the specialty oscillator chip can probably be eliminated as well and a single generic oscillator module can be used IF I go with the CPLD solution.
So, there are some very distinct advantages to going with an FPGA type chip.
I'll have a look at the website and see if I can learn anything, but it's tough for a non programmer to break into this sort of technology when very little is known about it from the start.
TTL output makes things a little more difficult, but 15MHz should be easy. I have no personal experience with the 3.3V Xilinx CoolRunners, but they
*mught* make it alone, or perhaps with a simple level-shifter. I'd have to study the sheets more to say.
Wasn't suggesting any of the kind (feachur creeps ;-). With 40-48 I/Os, you should have enough room for lotsa switches though. ;-)
Ok, what are your jitter requirements? Duty cycle?
Easy 'nuff.
Fechur creeps. ;-) These should be easy enough to make and gate.
Sounds like a plan to me! Pullups _might_ be an issue. The switches have to be powered by something. The CPLD I pointed you to was a 3.3V widget, so...
There are *lots* of advantages.
I'm no programmer. I'm about as much of a hardware type as you're going to find. I refuse to admit that I know how to spell 'C', and use assembly (any variety; new ones learned upon request) when I must.
The 3.3 v logic 1 will probably be ok driving 5 volt cmos. Keeping the frequency down would probably be wise in such a case.
Not sure about a number. But, the DDS chips have spurs and the PLL's have phase noise. The quadrature receiver is capable of very high performance and it's much easier to build-hardly any tuned circuits to deal with and is much cheaper to build as well.
So, quartz is still be best when one needs a high quality local oscillator. I want to use a quartz crystal with a divide by N to get the quartz performance and some minimal frequency agility (at LF receive frequencies) by varying the divide by N value.
It was my hope that starting with a clean quartz oscillator, then dividing it down would result in a high quality LO that would be similar in performance to the crystal alone and give me some minimal frequency agility.
The receiver I'm looking at is the softrock-40 unit shown
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I plan to convert the receiver to 160 to 190 Khz by dividing down a 30 Mhz crystal oscillator, which makes the LO easy to build and gives good performance in a small package. It does not allow the frequency agility of a DDS or a PLL, but I don't need the frequency agility anyway.
The duty cycle is of no concern, I just need an output that goes high long enough for the input logic to recognize the transition.
The 4059 (CD4059, HEF4059) is still available at some places, for about USD 3.00. To make it run at 15MHz, it requires a higher supply voltage of 10V to 15V, though.
On Sun, 25 Sep 2005 15:15:43 -0400, keith wrote: [TRABEM wrote] ...
I've downloaded Xilinx's "ISE" - I think that stands for "intelligent simulation environment" or something like that. It comes with some "examples" already done for you: Demo design for CoolRunner II demo board Sample EDIF Flow project Elevator design using incremental design flow Heirarchical Schematic project Frequence Meter XAPP 217: Gold Code Generator Bidirectional 4-bit Johnson Counter with Stop Control XAPP 211: PN Generator using Virtex SRL Macoro Pong game control for 3S200 Demo board XAPP 134: SDRAM Controller Demo design for Virtex2 Demo Board XAPP 258: 511x8 FIFO in Virtex2 Stopwatch Design for Tutorial
And you can input schematics, VHDL, Verilog, ABEL and/or EDIF. It has some pretty awesome tutorials, too.
I threw together a little bit of VHDL this afternoon, but made some assumptions (2x clock - 30MHz) to get a 50% duty cycle. I ran it through and *old* copy Synplify to get an idea of the timing. With even the old SPartanXL and Virtex FPGAs it claims better than 100MHz. I don't buy
100MHz, but 30 shouldn't be hard at all. I also told it to target some
*small* (and old) CoolRunner parts. It fit with oodles of space left, but I got no usefull speed information (I'm not familliar with the CPLD tools and the timing information wasn't where I expected it).
I haven't simulated it though, so may be off a count. ;-)
If you'd like a copy of the VHDL (I'd like to simulate it first), let me know. It really is simple (20 lines or so). I also have the equivalent schematics ("HDL Analyst"), but I'm not quite sure how best to post them. I didn't add your markers, but they're easy to drop in.
I found a 4059 for about $3. But, the 74HC4059 is much faster (although still not quite fast enough) and costs $1.60.
It's almost fast enough, need it to operate at 30 Mhz, but it's rated only for 28 Mhz with a 5 volt supply. Unfortunately, I can't change the supply voltage and 30 Mhz is bare minimum for my project.
I looked for an 74HCT4059 and a 74AC4059, both of which would be fast enough, but no one makes them (that I could find). Phillips used to make the 74HCT4059, but they have sold out to TI, who doesn't make them now.
I lied. It's 41 lines with all the necessary fluff. ;-) I'll post the VHDL later today (I'd like a chance to simulate and format it for the narrow screen). Some of the other files are graphics (print to PDFs). Those are interesting too and I'm not sure where to put 'em.
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