Hi,
Does anyone know how a clock can be divided by N, using purely combinatorial logic?
Thanks.
Hi,
Does anyone know how a clock can be divided by N, using purely combinatorial logic?
Thanks.
Gosh, it's so easy I feel dirty even mentioning type D flip-flops.
Getting a regular, specified duty cycle (such as 50%) for odd N is up to you, though.
Tim
-- Deep Fryer: A very philosophical monk. Website @
Perhaps the OP meant just using gates....
Yes I meant using purely logic gates, without flip-flops.
mentioning type D flip-flops.
a chain of flip flops long enough for your target N a little extra logic to trigger the lead flip flop on both the rising and falling edge of the input signal xor the outputs of the FFs with N nor the outputs of the xors and use that output to drive an output FF and reset the input FFs
Don't top-post.
And you can't build counters without flip-flops - a counter needs to remember data from the past, and that can't be done without some kind of memory device, which is to say a bistable, also known as a flip- flop.
You build counters from logic gates - which is to say, purely combinational logic - so the point is essentially academic, though it is tricky to build flip-flops that work reliably using off-the-shelf logic gates.
-- Bill Sloman, Nijmegen
Yes.
-- Many thanks,
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Yup, I think so, just nand gates or something. But it will have to have internal states, so some people might shout "flipflop!"
John
Another solution -- without flip flops this time !!
Clocked RS latches modified for edge triggering on the clock can be cascaded -- would take N latches and you can pick off your output anyplace along the chain to get any desired duty cycle. A clocked RS latch expands to
5 gates, and you'll probably need 2 or 3 more to make it edge triggered, which gets you riight up there with the flip flop for gate count per stage, but with the disadvantage of not using a counter approach which means many more stages for larger N.The question then becomes "just exactly HOW PURE" must the combinatorial logic be. If you cant build latches or flipflops from gates, I dont think its possible.
Just for grins -- here is a weird way to do it that just uses low level gates + some analog components
I think you can also just "walk" states through rs flops (or equivalent feedback gadgets) on clock high and low levels, which is not exactly edge triggering
The LC on the dflop thing is cute!
John
I've gposted cheap trick under the same subject line on a.b.s.e - it's out of the 7474 data sheet. ;-)
Cheers! Rich
Sure, it can be done. Just don't call your cross-coupled gates "flipflops"
- the professor will probably never know the difference. ;-)
(or you might lose points for coming up with a workable answer to what's otherwise an impossible task, in which case "it's impossible" might be the intended answer. ;-) )
Good Luck! Rich
build an N-counter in logic.
Where are you studying?
I was asked this question in a job interview actually. Thanks everyone for your inputs.
I agree--turning delay from a bug to a feature.
I built something similar to the rate-multiplier pulse swallower gizmo in my first engineering job, back in (ahem) 1982. It used two synchronously cascaded decade counters (LS161), and the rate-multiplier chain controlled the carry input of the less-significant stage. That dropped the jitter from 1 whole output pulse to about 0.015 pulses, which was a big help, since I was phase-locking a VCXO off the output.
Cheers,
Phil Hobbs
mentioning type D flip-flops.
There is a simple way to build reliable flip flops from gates. You use TWO flip flops per stage, a master and a slave.
The slave enters the change on one clock edge, and the master keeps it on the other.
How about this:
(1) Using five 74ACT inverters, make a slightly delayed and inverted version of the clock.
(2) Using another ACT AND the delayed and inverted with the normal clock to make a very thin pulse. The output of this AND is called OUT and is the output of the circuit. Use a 3 input AND for this to leave an input I'll call ENABLE below.
(3) Invert the OUT signal with a 7404. Don't use ACT here.
(4) Get a large number of TTL AND gates and wire them up to do the following with the inverted version of OUT (I'll write !OUT)
Y = !OUT AND (!OUT AND (!OUT AND (!OUT AND ........)))))))))))))))))
This Y signal is the enable.
I remember doing this back in the early days of PALs. I needed what amounted to a small counter, and I had unused circuits in a non- registered PAL on my board (16L8, I think). The boards were wirewrapped between DIP sockets, so changing circuitry was akin to crochet (I even used a crochet hook from the craft store to pull out deeply-nested 30-ga wires). I found that if I cross-coupled a few outputs I could get it to work like I needed. Only afterward did I realize I had made "logic-only" flip-flops.
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