PIC for clock divider?

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I was told to research if a PIC clock divider would be better or worse than
using a CPLD divider.  I would think that a combinatorial logic would be
more reliable than some software running on a PIC??  Also the jitter would
be less with propogation delay on discrete logic than a PIC??

We are looking to create a 10Khz clock from something much faster.  It needs
to be a stable/clean output.
Anyone have any comments or things I could research?


Re: PIC for clock divider?

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A uC timer can be used as an integer clock divider for moderate frequencies
(up to 10 or more MHz), and thats reliable and without jitter, if programmed
The main advantage is, that you can use the processor core for additional
purposes, and an available BOR (Brown Out Reset) for the whole system.
The clock to output time of the uC may be a problem, if not defined in the
data sheet.

A CPLD or FPGA divider can be much faster, with a defined tco, some FPGA's
allow zero tco with internal PLL's or DLL's.

Your selection also depends what you can do with the rest of the resources
of the CPLD/FPGA or uC.


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Re: PIC for clock divider?

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It depends on what you're dividing down from and your jitter

Small microcontroller (e.g. PIC) advantages:
  Long counters with a small (8-pin) chip.
  Essentially a synchronous counter.
  Not a ripple counter (phase modulation due to temp or Vcc effects
                                  on delays minimized)
  Easy to set "funny" division ratios.
  Often cheaper than CPLD's.

Small microcontroller disadvantages:
  Power-on reset and brownout recovery (many uC's like PIC's have good
capabilities here but you do have to think about it). To be fair these
issues come up to a lesser extent in "raw logic" dividers too in the
form of disallowed states.
  Firmware has to be written and maintained and loaded.
  Programmable device may be buried deep in hardware
  Raw (before division) clock rates max out in the 10's of MHz.

I cannot think of many places where the microcontroller wouldn't win.


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