Decoupling

I've always used parallel capacitors such as 1nF and 100nF to get good decoupling.

I have the impression this doesn't really apply with surface mount capacitors.

I'm redoing a 250kHz 5A charger design which has 4u7, 470n, 47n in parallel with the same the other side of a sm ferrite bead.

What would you do to keep crap in?

Reply to
Raveninghorde
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If you use a capasitor over its series resonance frequency it may resonate with smaller one and they lose effectiveness. This is what I read. Personally I have not noticed anything strange myself.

Reply to
LM

Are you trying to make the circuit work, or to keep noise from escaping to the outside world?

On multilayer boards that have power and ground planes, I just splatter some 0.33 uF 0805 caps around each power plane or pour. That keeps the power node quiet. The quieter your power plane, the less will want to get out.

In your case, what's on each side of the bead? If it's a power pour over a ground plane, just use a few biggish (very roughly 1 uF) ceramic caps. If you're trying to keep noise *in* (from escaping to the outside world) it would be good to keep the inside stuff quiet to begin with (ie, power plane with bypasses) and couple that through a bead or inductor to a small pour that has several bypasses of its own, a bypass island.

Tons of people advise the multi-value thing (like your 4.7u, 470n, 47n example) but I don't think they have a solid basis for doing so. In my opinion, in real life, the multi-resonance Spice models of paralleled caps that people love to publish aren't realistic. At 250K, use big caps.

I have never used too few bypass caps on a multilayer board, and I've been inching my way down over the years. On an FPGA with three supplies (core, i/o banks, aux) I/ve got down to three or four caps per supply, and that works fine. Maybe I'll try two next time.

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John Larkin, President       Highland Technology Inc
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Reply to
John Larkin
[snip]
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Those Spice models were of _leaded_ capacitors, not chip caps. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

If it's a simple series resonance, then it's symmetrical in log(f). Thus if the bypass is good enough at SRF/10, it's also good enough at

10*SRF.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs
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Reply to
Phil Hobbs

Good point, but... Though it's the same _impedance_ at 10*SRF it's inductive instead of capacitive, so YMMV. ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson
[...]

One can find that even on eval boards. Down to 1000pF or less, ridiculous. The resonances of a SMT cap are determined by the dimensions of its body plus trace and via lengths and shapes. So placing a 1000pF

0603 in parallel with a 0.1uF 0603 for decoupling doesn't make much sense. Except for the sales numbers of the cap manufacturer. [...]
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Regards, Joerg

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Reply to
Joerg

All of them, forever? Are you sure that nobody has ever simulated surface-mount bypass caps?

I've seen both, mostly surface mount in the last 20 years. Who uses leaded bypass caps any more? The modelers tend to write long papers that use naiive simulations of lumped R-L-Cs, and almost always ignore the PCB planes. The planes change everything.

I like to add SMA connector footprints to PCB layouts, so I can TDR the planes with and without various bypass caps soldered in place. That's instructive.

ftp://jjlarkin.lmi.net/TDR_3Vplane.JPG

The SMA also lets me measure plane noise when the built board is running.

Hmmm, on my next VME board, maybe I'll put SMAs in the center and the corners of some power pours, and see if I can better spot edge reflection effects. And do other stuff.

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John Larkin, President       Highland Technology Inc
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Reply to
John Larkin

Yes, though that's mostly paranoia, I think--people associate inductance with ringing, but that's wrong when you're above the SRF, unless of course it resonates with something else.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs
Principal Consultant
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Reply to
Phil Hobbs

I'll take a look and see if anyone has updated models to surface-mount. Discrete Spice modeling, active and passive, has lagged _way_ behind CMOS chips. It's extraordinarily rare to have a chip fault that Spice didn't catch.

...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

It doesn't matter that it's inductive; it's the absolute impedance that matters. At 500 MHz, a 10 nf 0805 cap will have about the same impedance as a 1 uF cap, even though the 1 uF has a much lower SRF.

Bigger caps are almost always better.

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John Larkin, President       Highland Technology Inc
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Reply to
John Larkin
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Looks like Kemet is making some effort to model the distributed inductance (watch the wrap)...

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$file/2010-03%20CARTS%20-%20Spice%20Models%20wTemp-Bias-Freq%20Concerns.pdf

I made distributed wirebond and package-pin models for Intel back in

1994. ...Jim Thompson
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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Reply to
Jim Thompson

Note that the co-authors of some of the most popular papers work for capacitor companies.

I've seen the claim that *every* power pin of an FPGA should have three bypass caps. That gets up to hundreds of caps per chip. I've even seen people do it! Garlic *does* keep vampires away.

I use about 3 caps per voltage for an entire chip.

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John Larkin, President       Highland Technology Inc
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Reply to
John Larkin

Just like oil companies recommend changing the oil every 3k miles. And Raytheon and Bosch recommend to swap the oil filter along with it. Oh, and of course you should swap the whole vehicle against a brand new one within five years, sez the sales guy.

My impression with some of the papers that recomend this cap-stagger is that the authors were either rookies or pure academians who barely know how to hold a soldering iron without ending up in the burn unit of the hospital.

At a client in Seoul they told me (dead serious!) that each day you fail to take in a good dose of garlic will shorten your life substantially. When I returned my wife almost banned me from the bedroom, despite the fact that she likes garlic. The stench was almost unbearable, she said.

Muntz would have removed two of them and told you "See, still works. Don't waste money" :-)

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Regards, Joerg

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Reply to
Joerg

According to some studies I've seen, the use of paralleled capacitors can actually be counter-productive, if they've got any significant amount of parasitic inductance in their design (e.g. if they're through-hole / leaded parts).

Each cap will have its own self-resonant frequency, at which its capacitance and its parasitic inductance form a series resonance. Above this frequency it'll present an inductive impedance across the power planes.

If you parallel a larger-value and smaller-value capacitor, there will very probably be a frequency (part way between the two caps' series self-resonant frequencies) at which the inductive impedance of the large-value cap (above SRF) and the capacitive impedance of the small-value cap (below SRF) will form a parallel resonance. Shazam... you now have a very high impedance across the power planes... in effect your bypassing just doesn't exist at that frequency, and is not very effective around it.

Unfortunately I did have a nasty experience with one board which had inadequate bypassing. It was a Boca PCI Ethernet board, built using the (quite good) AMD PCNet chipset. Unfortuantely Boca had ignored AMD's engineering notes on the part, and had only abotu 25% of the recommended bypassing... and they had omitted the "critically important" bypass cap on one of the chip's analog-side voltage supply pins. As a result, the board suffered from a nasty bit-pattern- sensitive voltage bounce during receive operations... most packets got through just fine, but some containing particular bit patterns would "drop a bit" and be rejected by the FCS parity check (almost 100% reproducible). Very frustrating!

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Dave Platt                                    AE6EO
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Reply to
Dave Platt

I used to work with a tech who'd attended someone's signal integrity seminar and came back convinced that every single signal pin needed its own ground return pin even when we were talking low-speed digital signals with rise-times in the ballpark of 10ns. He even felt that high-speed signals should perhaps even have two ground returns of their very own...

Since he also did PCB layout, we often ended up with larger and more expensive connectors than were really necessary IMO.

Ugggh.

Reply to
Joel Koltner

I don't care if the plane impedance is inductive or capacitive or resistive. I just want it low.

That the Spice thinking that you see all over the place. The people who do this tend to ignore the PCB planes.

Yeah, some chips have low frequency current steps, the classic being an Intel CPU that goes from low power to tens of amps instantly as the compute load changes. The bypassing has to be stiff at low frequencies to avoid a voltage dip. FPGAs tend to not do this.

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Reply to
John Larkin

=A0 =A0 ...Jim Thompson

=A0 =A0| =A0 =A0mens =A0 =A0 |

=A0 | =A0 =A0 et =A0 =A0 =A0|

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=A0 =A0 =A0 |

Thanks for the URL.

companies supplying incredible models: AVX Murata

Even ran across some S parameter models!

from memory of measurements:

  1. Keep power/GND planes really close, < 2mil, 5 mil for cheap, use several interleaved if possible Remember at extremely high frequencies the planes act like a transmission line injecting/drawing current that then 'spreads' out over the planes. See AppNote from Ansys regarding their HFSS simulations for a great explanation. Keep that spread out uniform by putting caps approx 1 per sq inch, and DEFINITELY caps outside your last active circuitry towards unoccupied board area and between circuitry and edges. I recommend using the SAME caps, I've seen poor distribution/placement and non-uniform selection actually raise the effective local impedance of a section of the PCB to over 10 ohms in a spectral band! Have a clock harmonic on top of that and you'll see the ringing!
  2. Don't punch holes in the planes! Holes do untold damage, and cut outs around vias should be minimal to 'lessen' this damage.
  3. Remember a board is really a capacitor with its OWN resonance, where the first resonance is usually approximated as a quarter wavelength using the longest, diagonal dimension in conjunction with the dielectric constant of the material, approx 4.2 for FR4. Also, remember FR4 is a 'quiet' material and your friend above 1GHz. A small board can go resonant as low as 500MHz.

I think also in an App Note from Ansys, there is a design example whereby they show that by judiciously selecting capacitors, placement etc, they actually IMPROVED performance by removing 12 of the 60 original bypass caps in their example. It showed how important it was to place caps near to where they were needed and important to NOT cut too many vias through the planes.

As anyone who works in RF knows, a connection is only a connection if it is wider than long, else it's an inductor [at some frequency]. AVX is FINALLY making their caps wider than long. Instead of metalized tube in an 0805 package, they have metal along each long side! Look at the associated specs to see the effect! But those COST a lot.

OPINION: From memory, SMT capacitor packages have similar inductances, so it is FAR more important to use the same size packages everywhere. Thereby, after the caps go through resonance, you have all the same value inductors in parallel, and parallel inductors have a low impedance, too.

Reply to
Robert Macy

Just a few minor things that come to mind:

Layers usually come down to 10 or 15 mil, I don't know how thin manufacturers can make it, but 2 mil seems a stretch, just for dielectric strength if you were you put any voltage on it -- not that you need to, for say, an FPGA's 1.2V (or less) core supply of course. I haven't heard of any that thin. Kapton flex circuits would be able to do that. The impedance would certainly be miniscule!

This isn't such a big deal -- to a point. Out of, say, a 2" wide board, the ~30 mil hole (with pad and clearance) around a fairly large via isn't going to interfere with currents traveling across the board when there's another

1970 mils left. The width of that hole, even if it were a narrow loop of trace, hardly has any inductance (ok, at UHF+ you'll notice a nanohenry here and there). There isn't really anywhere for the flux to go in such a closed space. Even if the ground plane is dotted with enough vias to reduce its cross section to ~1000 mil (i.e., 33 of those holes evenly spaced), there's still a lot of room between them to carry current; the reduced cross section increases resistivity marginally, but only for maybe 20 mils of length (roughly the width of the pile of vias), increasing resistance negligibly. Most likely, you aren't carrying really heavy currents across the plane anyway, making the effect that much more negligible.

Now, if you have a big row of vias, or some traces you can't route anywhere else, you're going to make a slot, which still doesn't leave much room for flux, but is an obvious obstruction for perpendicular currents, picking up more resistance and inductance, and can resonate at specific frequencies -- any traces crossing that slot can pick up nasties as a result. Stitching across any slots crossed by those currents or traces helps minimise this problem.

At any rate, the obvious conclusion: having one at least mostly-solid ground plane is damned hard to beat. The effective resistance and inductance of a connection drops to nothingness over a short distance.

Tim

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Deep Friar: a very philosophical monk.
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Reply to
Tim Williams

I've specified 6mil prepreg. One and two mil FR4 is available for flex circuits, as well. It has some properties that are superior to kapton.

The problem comes in with a lot of thru-hole components or vias turning the ground plane into a bunch of slot antennas. Be careful with hole spacing.

You make it sound like a rarity. ;-)

Unfortunatly I have to intentionally slot the ground plane on the design I'm doing now. It's at the edge where the RF lives. It's done for good reasons but I'm mostly in the one-ground-plane-everywhere camp.

Reply to
krw

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