I need to generate the reference voltage for a DDR3 design separately, i.e. I cannot use an integrated solution for VDDQ/VTT/Vref.
Following the recommendations in the EE-Times article "Powering DDR memory and SSTL logic" by Peter James
it is advisable to use an OpAmp for Vref generation.
In my design I have one memory controller (which has one sink pin to Vref) and 9 memory chips, which have 4 uA max leakage current each.
If I used a resistive divider with for instance 100 Ohms, the summed leakage current would add to 2mV, with respect to the 675 mV well away from the margins, and the load on VDD would be relatively low compared to the memory consumption. So I guess it is the dynamic load that requires the opamp. I try to get the capacitive load of the Vref pins (not in data sheets), but to select the OpAmp I would need to know what kind of AC component I have to deal with on the VDD. There is of course the rest ripple from the switching power converter that generates the VDD, I can estimate that. But do I also have to include ripple generated by varying current draw of the memory and the memory controller? That could have a high frequency. Of course tons of decoupling caps will be there, but they will not entirely clean VDD.
Any experience?
Andreas