Decoupling capacitors

I wonder about wisdom of paralleling ceramic decoupling capacitors. I some old text I have found advice to use 10uF (electrolytic), 100nF and 100pF in parallel. Several relatively new text write about combinations like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear: electrolytic is mostly resitive in middle of frequency boound and ceramic gives pure improvement. However, datasheets of modern ceramic capacitors suggest that ESL is almost independent of capacitance (ESL groves with size but in given size seem to vary only a little). Simple RCL model shows that parallel ceramics will have parallel resonace peak when capacitance differ enough (about 3 times for modest peak, 10 times gives substantial peak). Parallel combination will have smaller impedance above self resonant frequency of smaller capacitor but the gain is modest. OTOH close to resonant peak we will have substantially higher impedance. For me it does not look like good deal. In fact, when low impendance at high frequences is important it looks better to connect several nominally identical capacitors. With usual tolerances they should give no parallel resonace and lower impendace due to paralleling of ESL.

In principle one could play tricks with resonance frequencies putting parallel resonace at frequency not present in circuit and serial resonances at frequencies needing suppression. But with usual tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling different decoupling ceramics gives some advantages? Or is this advice about paralleling just repeating old lore without understanding that world has changed?

--
                              Waldek Hebisch
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antispam
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Am 10.12.20 um 15:55 schrieb snipped-for-privacy@math.uni.wroc.pl:

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cheers, Gerhard

Reply to
Gerhard Hoffmann

That looks roughly right, I didn't go into the details. As a rule of thumb, I count 5nH ESL for a radially wired capacitor with 2.5mm between the wires. It doesn't really matter if it's ceramic or electrolytic, although there may be unpleasant surprises sometimes. For ceramic multi-layer SMD capacitors, it's about 0.5nH, and it doesn't matter much if it's 1206, 0805 or even smaller. It's the aspect ratio that counts.

There may be some virtue in combining an electrolytic with an SMD ceramic, but paralleling multiple ceramic SMDs of different values is basically nonsense. Small electrolytics are useless for decoupling, because of high ESR.

Jeroen Belleman

Reply to
Jeroen Belleman

If you're designing fast stuff, use a multilayer board with a ground plane and power planes or big pours. The fast low-impedance bypass is the plane pours themselves. The ceramic caps just help out at mid frequencies, and it doesn't much matter where they are.

Some loads, like CPUs, can have gross low-frequency current surges so need a mot of microfarads somewhere. Polymers are good for that.

People like to draw graphs of ESR of various caps in parallel vs frequency, and argue for a lot of different values. That's mostly silly. The PCB planes are a great low-L, low-Q capacitor network.

I sometimes add SMA connectors to my board layouts, so I can TDR traces and planes. That wrecks a lot of hand-wavey Black Magic theory.

I use 1 uF almost everywhere. Too many, actually.

I saw one board being assembled for Anritsu, in a shed in Hamamatsu. It had 3000 bypass caps per board. Seems excessive.

There is some old Xilinx appnote that calls for hundreds of caps on one FPGA. It was co-authored by CTS I think.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

Am 10.12.20 um 15:55 schrieb snipped-for-privacy@math.uni.wroc.pl:

Istvan Novak has written many useful articles and books on power integrity.

You might have a look on his webpage:

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Cheers Michael

Reply to
Michael

Parallelling ceramics is good for very fast stuff, where the inductance of ground vias is important. Several 0402s connected to a ground pour with lots of via stitching is a big win then.

In power distribution via traces, you can get nasty antiresonant peaks if you don't have enough damping. In general the best advice is to sprinkle some largish Al-poly electrolytics on the rails. They work like lead-lag networks, and so knock down the parallel resonances very effectively. It's fun SPICEing stuff like that, and also reasonably educational.

Power pours are much less susceptible to resonances than traces are, because the current pulses injected into the planes spread out in all directions. In addition, the weak reflections that do come back have all different delays.

That's quite a different situation from a trace, where the reflections don't spread out in space or in time, but come back at you all at once.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com
Reply to
Phil Hobbs

Generally speaking, what is important in power supply decoupling is a unifo rm low impedance across the frequency range. However, if you don't have no ise at a frequency it is not important to have a low impedance at that freq uency in your power distribution system (PDS).

When you use a single value of capacitor in combination with a low ESR powe r plane, the inductances and capacitances form resonant circuits that creat e peaks and nulls in the PDS spectrum. These peaks and nulls are mitigated by the ESR of the capacitors, so are limited in magnitude. As long as the frequencies of the peaks are not at a harmonic of your noise frequency, th ey won't matter. If you need to mitigate the peak of one capacitor value, you can use another value/size cap with different ESL which will create oth er peaks, but those resonances will be in parallel with the original circui t nominal impedance and so greatly reduced. Some people even add a third v alue of cap to mitigate the peaks further.

This is all very murky since the ESL is often not a well known value and th e characteristics of the power planes are often not well known. One issue that is pretty clear is the spacing between caps and power pins. What is i mportant is maintaining short distances between the caps and the connection to the power planes and the power pin connections to the power planes. O nce connected to the power planes the spacing between the power pins and th e caps is not so important as the power planes act as a transmission line c onnecting them. While the impulse of a current spike is working its way to the capacitor, the power planes provide the current needed by the power pi ns. It's a great image that shows there is no need to try to calculate the loop area, etc. Just provide good connections to the power planes and the rest just works.

--

Rick C. 

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Reply to
Rick C

Interesting. AFAICS all parallel combinations of ceramics added resonace and had worse result than single ceramic. But curiosly, you checked 0.1uF and 100uF but did not check single ceramic in

1uF to 20uF range (which looks like optimal range for good decoupling). Also, electrolytic in parallel with single moderate capacity ceramic is very natural.

Concerning parallel connection, I do not see measurement with identical ceramics in parallel. Another things is distance between capacitors. Comparing page 6 and 7 suggests that small distance between capacitors give better decoupling, but what about bigger distance than what you had and the same capacitance (natural case when several IC-s each have its own capacitor)?

--
                              Waldek Hebisch
Reply to
antispam

snipped-for-privacy@math.uni.wroc.pl wrote: ...

If you want broad range loew impedance, consider feedthrough

Bye

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de 

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt 
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------
Reply to
Uwe Bonnes

Gerhard, I think you'll find it's easier to read the exact self-resonant frequency of the cap by putting your VNA in phase mode and placing your marker(s) on the cross-over point.

Reply to
Cursitor Doom

you can also get capacitor that are "rotated" so they short and wide i.e. 0306 instead of 0603

Reply to
Lasse Langwadt Christensen

You can't have too much stability in a highly delicate and sensitive piece of test equipment, though!

Reply to
Cursitor Doom

From your site:

"The 60 mm of wire make quite a mess. Now think if you trust C measurements on those multimeters with unknown frequency and long cables."

We seem to have gone backwards. 40 years ago I bought a multimeter with LCR from Maplins or Conrad; can't recall which one (so hardly a specialist supplier!) and it had a very useful square centimeter of breadboard at the top just for directly plugging in caps and coils. I haven't seen one since in all those 40 years.:(

Reply to
Cursitor Doom

In a former employment, a large board with over 1000 caps had a production issue, so no caps was mounted. The board worked anyway due to the Stackup as Larkin explained

Lee Ritchie has a book where he travels into the details, "right the first time" I think it is called

Cheers

Klaus

--
Klaus Kragelund
Reply to
Klaus Kragelund

A colleague had all kinds of trouble with such paired capacitors resonating around 900MHz in a specialised receiver for 144MHz. When you get parasitic power plane oscillations far above the frequencies you're expecting to see, it can be very mystifying.

CH.

Reply to
Clifford Heath

torsdag den 10. december 2020 kl. 17.33.38 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

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Reply to
Lasse Langwadt Christensen

I don't think I have ever used too few bypass caps. Always too many.

I know one guy who didn't use bypass caps on digital boards, and his stuff worked.

A lot of big digital ICs have on-chip supply bypass caps. I measured an FPGA that had several, the biggest being a few hundred nF. That takes care of the high-frequency stuff.

But some, like the ST ARMs, don't.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

That is wonderfully bizarre. What is it?

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

We use those in fast signal paths. With luck, one exactly spans the width of a trace.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

fredag den 11. december 2020 kl. 01.56.09 UTC+1 skrev snipped-for-privacy@highlandsniptechnology.com:

graphics card,

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Reply to
Lasse Langwadt Christensen

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