frequently I see suggestions that ICs etc should be decoupled by, for example, 1nF, 10nF and 100nF in parallel. Is this just a hang over from PTH days or is there still some advantage in doing this with surface mount X7Rs?
Three separated by only a decade is nuts. If you have power and ground planes one is usually overkill but I generally put one (100nF) per just to get the footprints on the board. Larger chips get more, as recommended by the manufacturer. Sometimes I'll add a couple with a SRF at the frequency of interest if I'm worried about EMI from the chip. Caps are cheap, deleting them from the BOM is even cheaper, adding them later isn't.
Unless the manufacturer has specific recommendations, I use one 100nF cap per power lead on the chip, then as much bulk capacitance following the power supply as it needs for good behavior.
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Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
On a multilayer board with a solid ground plane and big power pours, just the occasional bypass cap here and there works for most situations. I don't think I've ever done a board that had too few bypass caps. I should use less.
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John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
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It never made much sense. If you need a lot of decoupling, a 10uF tanatalum is handy and has the advantage of having enough ESR to damp the resonance between the high capacitance and the significant loop inductance.
Back when I was being ultra-careful, we bought 1nF porcelain microwave capacitors, which looked capacitative all the way up to 1GHz (IIRR) and used them to provide extra by-passing for GigaBit Logic's GaAs, but never went to the trouble of finding out if they made much difference.
John Larkin doesn't think that it was worth the trouble, and he's the guy who's got recent hands-on experience with logic that runs just as fast Gigabit's GaAs did.
Hmm, possible. Back then, a 1nF was physically smaller than 100nF, so the ESL was lower.
Today, they all fit into the same 0603, even 0402 at low voltages, so as soon as Xc --> 0, impedance is dominated by ESR and ESL, which are geometry defined. ESL is by length / width, while ESR is by electrode resistance (and some from dielectric losses).
Simulating a crude backplane is illustrative. More caps can actually make things worse, with staggered values or otherwise.
Aluminum polymer caps are generally a bad thing, because their super low ESR enhances the resonances due to ESL. Standard tantalums are perfect because they tend to damp things, as Bill said. Special low-ESL tantalums fall somewhere between alpoly and regular, probably on the low side for most purposes. (Save the low ESR caps for where it matters: power supplies with big peaky currents!)
To give you some understanding of the system, the ground plane generally looks like a short circuit across its width. It has very low inductance between points, and a small capacitance to ground, which dominates at high frequencies (over 50MHz or so). The sheer existence of the ground plane dominates HF performance, and in many cases you might easily survive without any tiny caps at all!
When you add a bypass cap, it pokes down to the planes with vias. The via-cap-via loop is on the order of 2-3nH. This is worsened with connecting traces. Via pairs, placed directly aside the pads, with minimal trace length, are best. Since Xc --> 0 at high frequencies, any cap looks like an inductance, which makes the ground plane's capacitance resonate -- *worsening* things!
When you add a cap with ESR, it acts in parallel with the ground plane C. This resistance has to be connected with a sufficiently small ESL, so ESL must be very small on the damping components. Thus, you want to use a few, scattered about (where doesn't really matter!), and perhaps use extra vias with them.
You could easily distribute 100nF's with 1 ohm chip R's to accomplish the same thing, but you might as well take the additional bulk capacitance in stride.
When low noise is desirable (or required!), of course, you'll want a good bit of ESL between the noisy PSU and the ground plane. Ferrite beads are handy little buggers.
Tim
--
Deep Friar: a very philosophical monk.
Website: http://seventransistorlabs.com
I had a GBL data book, and foolishly tossed it out in a major cleanup, when we moved across town. Early 90's, as I recall. Wasn't it depletion-mode gaasfet logic, like the old depletion-load nmos stuff, like an MC6800? Power hog.
Was the GBL stuff reliable? Lots of early gaas wasn't.
On multilayer boards, we just seed the power pours with some 330nF
0603 caps, wherever they are convenient. That works for 40 ps CML edges, and works with brutal FPGAs, too.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
I like polymer aluminums. The low ESR is great for holding up things like Vcc_core of a uP or an FPGA, with transient loads.
We use a United Chemi-con part, 180 uF 6.3 volts surface mount.
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Rough numbers are
ESR = 15 mohms
ESL = 5 nH (!)
Series SRF = 170 KHz
Xl at SRF = 5 mohms
Q at SRF = 0.3
That's pretty close to a perfect capacitor. It won't explode like a tantalum and won't freeze like a regular 'lytic.
I suppose I could do something similar with a few ceramic caps; people make 100 uF parts these days.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
They're pretty amazing. The only downside, as far as I know, is they get steamed to death. In a manner of speaking. Specifically, inevitable moisture *ingress* degrades the dielectric, increasing leakage or reducing capacitance or voltage rating, or something like that.
And as you've noted before, dielectric failure isn't usually a bad thing, they tend to self-heal at about twice rated voltage.
Also, you don't have to pick a 2-3x safety margin on operating voltage, like you do with tantalums.
Still, MTBFs in the >10khr range, for reasonable ambient temperatures (
Mine is dated 1989. And I was sentimental enough to ship it out to Sydney, despite the major clean-up when we moved countries.
stuff,
It was source-coupled logic, very like ECL, and equally greedy of power. The data book talks about depletion mode FETS, but says they were set up to produce enhancement/depletion mode FETs too. We mixed it with 100k ECL - they were compatible.
Worked fine for us. Of course I'd taken the precaution of improving the control loop stability on the Cambridge Instruments/ Metals Research GaAs crystal pullers (used to produce 95% of the single crystal GaAs made in the West at the time) the previous year. Admittedly replacing a 741 with an op amp without pop-corn noise did take much inspiration.
might have been thinking about 'stitching' across a boundary. for those GPS, Bluetooth, Wifi, zigbee, or GSM or the multi Gbs boards which require surface GND planes - well sometimes.
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