Decoupling

Many of the newer FPGA families have decoupling caps inside the package. Whilst the datasheet may not explicitly explain this, you can tell by looking at the decoupling guidelines from the manufacturer. If the guidelines say you need nothing smaller than 470nF, it's a sure bet that they have something inside the package to handle the higher speed stuff.

E.g. for Xilinx Virtex 6, UG373 says: VCCINT: 4 x 330uF VCCAUX: 4 x 47uF VCCO: 1 x 47uF (per bank)

Regards, Allan

I agree. The planes act as an extremely low inductance capacitor parallel to the decoupling capacitor. All it comes down to is the inductance in the trace and via. This assumes you get the planes right though.

When I start a board with high speed digital stuff the first thing I do is to organise the copper pours for the power planes in combination with component placement so that the pours are wide and uninterrupted. Sometimes this leads to less than obvious component placement.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
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The planes at low frequencies work quite well. At high frequencies the planes act like a transmission line, with a Zo(f). And, the only way to lower the Zo is to move those planes CLOSE together. High speed is the 10-100 Gbs stuff.

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Tim, 15 mil is only a 4 layer board. Boards routinely are 12 to 16 layers and still 62 mil thick total.

Even two years ago, 6 layers in a 32 mil baord, only reason the layers were so thick was to be able to go cheaper offshore later.

Breakdown is incredible on these materials. From memory 500-600 volts per mil. but the most breakdown occurs at edges, sharp points, etc. Even at the thinnest, you have over 50 volt breakdown.

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Your calculations suggest that there should be no problem punching holes in the planes, but...there is.

A GND plane is like a dead short, BECAUSE currents can flow everywhere. Thwarting that process raises the plane's impedance. I have a plot of GND plane currents showing current coming from a microcontroller 200mA and as the current goes into the gnd plane via it spreads out, the voltage profile around the via looks like a teepee. Yes, current actually flows AWAY from the battery supply for a bit, then turns and starts flowing TOWARDS the battery terminal. It is due to these 'weird' flow patterns that must not be interrupted that raise the impedance, not the simple calculation of ground plane area.

From memory, a PCB can put a high speed line either on top the PCB, called a microstrip transmission line, or place the trace inside, between two layers, called stripline transmission line. One would think, of course a microstrip radiates power BECAUSE some of its field is outside extending into the air. and the stripline should not radiate anything beacue it is totally BURIED. But not so, any EMC test lab will show that a line on top versus a buried line only drops the radiation about 14 dB, BECAUSE of all the little vias/holes in the planes.

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True. Single gnd plane is hard to beat, but sometimes....I can send you plots of a sample PCB approx 3 by 5 inches board showing the return currents from the microcontroller and how much they affect the ADC, 24 bit isolated on a [yes, it was necessary] peninsula of gnd plane. Cuts WERE necessary to get the noise down below 1/4 LSB. But Usually I'm a SINGLE gnd plane person, until you get back up to 10GHz

+, then you have to start playing games again.

A plane pair is theoretically a big transmission line. It's weird because we access it at essentially a point interior to the big sheet transmission structure, at very hige speeds compared to the length/width; we don't normally do transmission lines that way.

If you put an SMA in the middle of a power/ground pair on a pcb, and TDR it, it looks, grossly, like a very good capacitor. If you really zoom up, you can see that it has a characteristic impedance, low ohms depending on spacing, and you can sort of see some edge effects, but the transmission line is actually pretty lossy so there's nothing dramatic. As you add bypass caps, it gets better and better, looking more like a pure capacitor.

People make a big deal over bypassing. On a multilayer board with planes, it's usually not a big deal. Almost anything reasonable works.

I do the same thing, but time domain.

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

The problem with boards like this is trace impedances. A stripline trace midway between two planes that are, say, 8 mils apart, is 50 ohms when it's only 3 mils wide. A 16-layer, 62 mil board would be close to impossible to do in FR4 and have reasonable inner-layer impedances.

--

John Larkin, President       Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

The question then is, if your current draw is so large and sudden, can you do anything about it at all? For the first few picoseconds, the transient propagates along the pin, trace, via, and the first few bits of annular ground plane (the very peak of the 'teepee', where voltage drop is highest). If that's not good enough, can you get a capacitor close enough so it is?

If we're talking nanoseconds instead of picoseconds (more likely with a microcontroller!), then nothing will happen so quickly and all that stuff will look like a tiny inductance. The question then becomes, if most of that 'teepee' is such a low impedance that we don't really care, how many wedges can we cut out of it until we do care?

For generic logic and small chips, it's not going to matter; most of them can be maybe an inch of trace away from a bypass cap, lots of leeway there. A big microcontroller or FPGA that's sucking fractional or whole number amperes in a few nanoseconds is a lot more critical, and you want to keep slots away from them. And direction matters, so a radial slot is better than a crosswise slot, etc.

Not at all surprised. Not only do currents spread out, but if you have the least current flowing sideways across that ADC, it's going to go nuts. Just because your ground plane is microohms doesn't mean miliamps won't generate nanovolts, and whoops there goes a bunch of LSBs.

Some people say cuts in ground planes are a good idea. Some people say it's the worst idea ever, and insist on solid planes. The smart people know reality is somewhere inbetween, and following the current flow, like following the money, always gets you the answer.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

Oodles of them. Not the easiest site to navigate, so I snagged the lot, using wget a while back.

Ten megs of zipped files.

--
"For a successful technology, reality must take precedence 
over public relations, for nature cannot be fooled."
                                       (Richard Feynman)

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I would expect 'some' effect. Check out Ansys HFSS example, it's a great tutorial for HIGH SPEED layouts.