:>> I am designing a homebrew double sided PCB. My only experience were from :>>DOS TANGO years ago. The board is half done and any recommendations are :>>welcome. I don't want to know that I am making serious mistakes when the :>>board is done. :> :> What sort of clock speeds and/or edge rates are you using?
: The clock is 20MHz. The DIP 20pin chips are 74LSXXX, the CPU is 80C188XL. : Other big chips (EPROM, SRAM, SCSI controller, UART controller) are all : slow. Their edge rates are mostly from 5ns to 10ns, or longer. The two : small chips are 74alvt16244/16245, their edge rates are faster, maybe : around 2 ns. The blank place will have a Altera EPM1270, whose edge rate : can be programmed to be several ns.
I think you should do (at least) a 4 layer board, with this stackup:
Sig (Vertical) GND VCC Sig (Horizontal)
This will help you for a couple of reasons:
- You are going to run out of routing space soon, given that you've got so many multi-pin components. Going to four layers will help a lot.
- Your rise times are not slow, at least your power distribution network. As you have it now, each VCC track is a big, long inductor, and you might couple glitches from one device to the next, or from VCC to a signal net via crosstalk. Use Power and GND planes to aviod this problem.
- Also, your current PDS (power distribution system) will radiate a lot since both your VCC and GND are just long antennas. Having a GND plane will help a lot.
- I don't recall seeing decoupling caps. Place one ceramic 0.1uF cap at the top of each DIP, and several around your BGAs. In fact, you can profitably throw the caps inside the middle openings of the BGAs, on the board's back side. Also, scatter some 4.7uF tantalum caps around your board for bulk decoupling. Again, this technique requires a power and GND plane in order to work. (If you did have decoupling caps which I didn't notice, then carry on as usual . . . . .)
I believe you are using gEDA/PCB, right? You can do up to 6 layers with PCB; the only reason not to is cost, whcih isn't that much compared to the price of an FPGA. And 4 layers is certainly cheap compared to a respin necessitated by signal integrity problems on your PDS.
Stuart