That works for *very* small entities. As I said in another post, this is really useful for seeing what muck the synthesizer is making out of your code. Synthesis uses "template matching" so one style of code *usually* produces one sort of output. These tools are great for discovering these templates.
I haven't found this sort of thing useful at all. The wires turn into spaghetti on very simple designs. The purpose of documentation is clarity, not spaghetti.
Haven't used it. Do you have a review?
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rickman
I have no idea why your gut feels the way it does. All you need to do is gin up a simple spice circuit and check its response vs. frequency.... at high frequencies, say 100 MHz to 5 GHz. You will see this clearly. The idealized circuit does perform worse than a real circuit because this is one of the times when the parasitic effects can help you. The ESR of the cap prevents it from having a sharp Q and a very high impedance at resonance. But it will have a resonance and it can easily create a problem at some specific frequency.
The seat of the pants analysis you gave has nothing to do with the resonance effect. In fact, you seem to think the inductance of the bypass caps "isolate" them from a resonance effect while it is this inductance that *creates* the resonance when coupled with the power planes capacitance.
Please do some searches on power supply decoupling and resonance effects. I am sure Lee Ritchey is not the only person who knows about this. I heard it from others before him, but didn't take it seriously.
One thing about power supply system design and decoupling... it is not hard to make one that works. But to know that it will work before you build it, that takes some knowledge. The old rule of thumb of adding a cap per power pin is pretty useless. So too are all the other "guidelines" that aren't based on theory, simulation and testing... all three. There are lots of things that may sound good until you actually verify them. The single most surprising fact I got from the high speed digital design course was that not only are much fewer caps needed than expected, but they don't need to be especially close to the power and ground pins of the chip!
Rick
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David Brown
Yes, that is pretty much how I thought - but you have given me cause to think again. I will have to take your advice and try some simulations - that's probably the best way for me to see what's happening, where the resonances are coming from, and the sort of effect they have. Until I have proved otherwise, I'll take your word over my gut feeling here.
The thing about searching on-line for this sort of thing is that there is no consistency in the answers. Either there are several different ways to do good bypassing, or the reality is that it doesn't matter too much. But it's easy to find "experts" (some of whom may actually /be/ expert) advocating multiple large power planes, or no power planes, lots of capacitors or few capacitors, lots of capacitor values or few capacitors, capacitors placed on the backside under the component or capacitors just roughly in the neighbourhood.
A bit of spice simulation is what I need here.
On the boards I have worked on (which were not more than about 200 MHz), I didn't have nearly as many as one capacitor per power pin, and I scattered them around to a fair extent. So my "gut feeling" gave me a similar result in the end.
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rickman
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Once I took Lee Ritchey's course, I realized that as you say, the experts disagree on how to design power delivery systems. So now when I hear someone, no matter who, say something about a topic, not just power systems, I look behind what they are saying at the proof. If it isn't there, I view it with a cautious eye. For power delivery, check out Lee Ritchey's web site called, "The Speeding Edge". They sell a book which I think has been updated and/or expanded since I took the class. It may be well worth the few bucks it costs. Even better, and much more expensive, is the class. If you are local to where it is being presented, I think the class is only a kilobuck or two. I found it well worth the money although it wasn't my money...
u
200 MHz is actually pretty fast. The edge rate of a 5 ns clock has very high freq harmonics. That is what you need to be concerned about. If you did well on that design, then you must have done something right. But in the real world just because your design worked, it doesn't mean your approach is always sound. I still don't have as much confidence in applying these ideas as I would like. But then most designs don't need all that much attention to power. The question is how do you know unless you actually do the math on the entire board?
Let us know what find in your simulations.
Rick
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David Brown
I've read a few things on "The Speeding Edge" - there was a lot of good stuff there. Maybe sometime I'll get the book, though I already have too many text books on my shelf waiting to be read! And I doubt if I'll make it to class - I don't think Norway counts as "local" in this case!
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John Fields
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Jan Panteltje
On a sunny day (Thu, 16 Dec 2010 09:27:00 -0600) it happened John Fields wrote in :
These go to 10V, the original 555 is limited at 18V IIRC, should work normally at 12.
Not sure if that does not rule out a lot of applications.
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John Larkin
Awfully expensive.
I used a 555 just once, maybe 20 years ago, as a charge pump driver to make a small negative voltage. It worked OK, but took a lot of parts: RC for the oscillator, power bypass for the 555 spikes, 2 caps and 2 diodes in the doubler. We don't even stock it these days.
We rarely make a board that doesn't have an FPGA or a microprocessor, or both. There's not much reason to add a discrete timing gadget.
If we do need an RC oscillator, we use a TinyLogic schmitt. We're paying 3.7 cents for an NC7S14.
John
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John Larkin
Yikes, expensive!
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I can get an ARM microprocessor for less than some of these parts. And it will have a pretty accurate internally-trimmed clock, and all sorts of other stuff.
John
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Raveninghorde
555s 12.5 cents 1000+. You can get an arm for that? I'm moving to the US!
Not that I disagree that it is normally cheaper to throw a micro into a design than use a 555 and a couple of other cheap chips.
Mind you some people program in Basic. We all get stuck in our comfort zone for some things.
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Arlet Ottens
Cheapest ARM at digikey, the LPC1111, with 8k Flash, 94 cents @ 1000+
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John Larkin
I wish I had problems simple enough to solve with a 555!
I program in Basic when I can, which is mostly under Windows nowadays. I have minions who program ARMs in C.
John
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Raveninghorde
True.
Which would you prefer for a produciton change, changing resistor and capacitor values on a 555 timer or a firmware upgrade?
And which one is easier as a field upgrade?
As I said we all have our comfort zones. Yours is Basic mine is the PIC. Time I looked at the ARM.
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Raveninghorde
I've stuck with PICs because they never obsolete a part without a plug in replacement.
I stopped using 8051 family parts because Siemens and Philips dropped parts leaving my designs obsolete.
So what are ARMs like for product life? NXP was Sigentics/Philips so I'm distrustful of their parts if single sourced. Maybe that's a reason for using the 555!
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John Larkin
The firmware! We can send our customers plugin eprom or serial flash chips, or just files they can flash themselves. Late last week we solved a problem in Ireland by emailing a flashable file that upgraded both the product uP code and the FPGA configuration.
ARM seems to be winning the embedded sockets, and maybe the desktop/tablet wars too. The 32 bit screaming fast architecture is sure nice.
John
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krw
We just post the firmware and an app to install it on the web. It's a lot easier letting the customer manage their upgrades/fixes.
I'm trying to get the firmware types to switch to ARM. After that, I'll sweep it into the FPGA. ;-)
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Spehro Pefhany
83 cents from Avnet in 500 quantity. Pretty amazing for a 8k flash/2k RAM 50MHz part with 10-bit ADC.. and if you want to do timing, its internal 12 MHz clock is accurate to 1% (including temperature and reasonable power variations). Wimpy 4mA outputs though. 28 of them.
Best regards, Spehro Pefhany
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
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John Larkin
But if you're driving other logic, you don't need terminations!
John
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John Larkin
We don't have that many customers, and field upgrades are rare, and we like to control the config of the units in the field.
But many of our customers can't receive zip files by email. Sometimes you can rename them .zap or .txt, but most of the firewalls have wized up to those tricks. So we ship them chips or CDs, or put the file up on an ftp site for a while.
The new Actel chips look interesting: FPGA, hard ARM cores, analog, all on one chip. The problem with putting a real CPU on chip with an FPGA is that you can run out of ram, already a scarce resource, and have to go to external dram+cache, which gets to be a nuisance and takes a lot of pins.
John
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Joel Koltner
I really have to wonder about the IT departments that won't let you receive .ZIP files via e-mail but are perfectly content to let you download whatever you want from an FTP site. In both cases you have to actively "engage" (un-zip the file or initiate an FTP session) before any executeable file could, um, execute anyway...
I'd also worry about how well the analog bits can do with a fast CPU or FPGA logic sitting just a few microns away. ...but I suppose the answer is often "good enough..."
---Joel
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