cool BGA pattern

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All that beautiful room for vias.

John

Reply to
John Larkin
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"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

I could swear that edges are pulsating. Neat effect.

Cheers

Reply to
Martin Riddle

Very nice (the pattern - I don't have any use for the chip !). I wish more semi compnaies would think a bit more about the cost of using BGAs before connecting evey possible ball.

Michael Kellett

Reply to
Michael Kellett

The Altera chip we're going to use [1] is a solid rectangle of balls. Yuk.

John

[1] We're migrating away from Xilinx. Great silicon, insanely broken software.
Reply to
John Larkin

Were you doing anything "strange" with the Xilinx software? For example, running on Linux rather than Windows, or trying to use make rather than pushing buttons on their GUI?

Is Altera's software any better? (Are you jumping out of the frying pan into the fire?)

--
These are my opinions, not necessarily my employer's.  I hate spam.
Reply to
Hal Murray

They're not all that bad. Most of the center are power/ground so easier to wire. The problem is that without the doughnut hole there is no convenient place to put decoupling and terminators (on the back). The coarse pitched parts (1mm and .8mm) aren't hard to fan out, either. We're stuck with them because of our SMT process anyway. My problem is that no one makes low-pincount parts with a coarse pitch. They insist on .5 or even .4mm!

I didn't have a lot of problems with Xilinx, other than it constantly wanted to rebuild my libraries in a new location. I like Altera's software much better, though.

Reply to
krw

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There's a HUGE difference in package design for consumer products like mass-market microprocessors and PC chip sets, and embedded products like FPGA's and microcontrollers. For the consumer stuff the overall package size isn't as important as the ability to lay out the circuit on as few layers as possible. For embedded components its ALL about package size. The boards just keep getting smaller (look at cell phones). On a board the size of a PC motherboard, you don't want 12 layers, or fine pitch routing, or blind vias... Much better to have a 12-layer BGA substrate that brings out signals to 1.27mm spaced pads in an order that matches the surrounding chips so that the entire bus routes in one or two layers. But you can clearly see that these BGA packages are significantly larger than the silicon devices they support.

On a cell phone sized board adding a couple layers or using blind vias or microvias won't increase the product price significantly. But having a chip that takes up the entire board would be a design killer.

Regards, Gabor

Reply to
Gabor

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I wouldn't rush a decision like that - especially when I know from a very good source that there is a major effort underway to improve the SW at Xilinx. I hear there is a upcoming version of the SW that will be a big step forward in terms of quality, speed, etc. So might be worth waiting a while, especially if you are familiar with the silicon already.

Reply to
2cents

Do you still believe in Father Christmas and the Easter Bunny too?

Jeroen Belleman

Reply to
Jeroen Belleman

That's not surprising. You could say the same about Microsoft. The issue is that software, and software culture, can be so broken that it can't be fixed.

Then why aren't our FAEs telling us about it? Maybe because Xilinx fired all of them not so long ago.

John

Reply to
John Larkin

It's easy to be dismissive - but believe it or not, Xilinx has been doing something about customer complaints regarding the SW tools. They have been working on the problem for a number of years. Have you seen PlanAhead? That's a taste of things to come, or so I'm told.

Reply to
2cents

Planahead is a tool which they've acquired. If the same group is developing ISE 13, it would probably be an good improvement. The main problem with the tools is timing engine and constraint management. If the timing engine under trace & par is replaced with something which supports SDC that would solve most of the problems are having.

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Reply to
Muzaffer Kal

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From page 26 of :

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_PlanAhead.pdf

Adoption of Synopsys Design Constraint Tcl Infrastructure

In the 12 release, the Tcl infrastructure in PlanAhead changed to accommodate the long-term plans for Xilinx to migrate toward Synopsys Design Constraints (SDC) for timing constraints.

Regards,

John McCaskill

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Reply to
John McCaskill

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I guess we can say "There is a Father Christmas after all ....." I think we'll all be much happier with ISE 13. Big companies can do great things when motivated, and from what I hear, Xilinx are very motivated in this area.

Reply to
2cents

This grumpy old man says "Harrumph".

Version 11 was NOT an improvement from version 10. I know of at least one design that works "just fine" when built with ISE-10, and fails to run with ISE-12.

Version 12 is NOT an improvement over version 11. My current project works "just fine" with ISE-11, but ISE-12 fails to build a bit-stream.

After two steps backward like this, I find your claim hard to believe.

For what it's worth: I find it to be about the same level of difficulty to switch ISEQuartus as I find it to switch ISE-(n)ISE-(n+1). And (with very few exceptions) by the time you get a feature out of Coregen/Megawizard, they all look the same.

Back to the OP's original topic: Yeah, these new packages are tough. Good thing itty-bitty ceramics come in large values, and thank the heavens for 'via in pad'.

RK

Reply to
d_s_klein

We just splatter a few 0603 caps on the top side of the board, far enough from the FPGA that production can get their little optical inspection gidget in there. Works fine.

Is via in pad safe? Is solder slurping a serious issue? I'd sure like to eliminate those dogbone things.

John

Reply to
John Larkin

Nonsense. There are many places where large packages aren't useful. Think: cell phones.

Cell phones aren't "consumer stuff"? You're confused.

I have no idea what you're talking about. You have it all inside out.

Reply to
krw

I saw this earlier on the TI OMAP35x, in a slightly different pattern (and smaller chip of course). They called it "via channels". Came with a guide on how to do complete BGA escape using 5/5 traces on 2 signal layers using 18 mil ring vias (I think), I like the effort.

It worked in practice when I did that layout too, but the actual pinning of the DDR-interface was far from optimal together with the LPDDR chip I used at least. Thank god for pin-swap on the buses :)

/Bjorn

Reply to
BW

No first hand experience, but I'm told if the vias are plated shut there is no solder slurping.

More interesting to me is the decoupling capacitor issue. I took a class on high speed digital design once and the instructor claimed decoupling caps do not need to be as close as possible to the chip to be effective when power and ground planes are used. In essence the planes provide the current the chip needs as the wave front propagates to the cap. Certainly the trace from the via to the cap should be as short as possible. I believe that is what you are saying works for your dense BGAs.

He did also make a case for using multiple values of caps to minimize resonances in the power decoupling circuits. BTW, he didn't just hand wave this stuff. Everything he told us in class was analyzed in theory, simulated in software and then tested in hardware. Lee Ritchey of Speeding Edge consultants.

Rick

Reply to
rickman

No first hand experience, but I'm told if the vias are plated shut there is no solder slurping.

More interesting to me is the decoupling capacitor issue. I took a class on high speed digital design once and the instructor claimed decoupling caps do not need to be as close as possible to the chip to be effective when power and ground planes are used. In essence the planes provide the current the chip needs as the wave front propagates to the cap. Certainly the trace from the via to the cap should be as short as possible. I believe that is what you are saying works for your dense BGAs.

He did also make a case for using multiple values of caps to minimize resonances in the power decoupling circuits. BTW, he didn't just hand wave this stuff. Everything he told us in class was analyzed in theory, simulated in software and then tested in hardware. Lee Ritchey of Speeding Edge consultants.

Rick

Reply to
rickman

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