-- No. The spec states that the "0" input level which is guaranteed to switch the output will lie between 1.5 and 2.25V and that the "1" input level which is guaranteed to switch the output will lie between 2.75 and 3.5V. The area between 2.25 and 2.75V is undefined.
Maybe I'm reading it wrong, but to me the only "guaranteed" switching points are at 3.5V and 1.5V.
[snip]
Not hardly. I design in CMOS or BiCMOS every day.
Read it again. "Typ(2)" Read the note.
Believe whatever you like, you're not a significant player in this action anyway ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC\'s and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
-- Yup. I misinterpreted the "typicals". With a 5V supply, if you drive the input to somewhere between 0V and 1.5V the output is guaranteed to switch, and if you drive the input to somewhere between 3.5V and 5V the output is also guaranteed to switch.
Since nfets are a little friskier than pfets, most cmos parts have an actual threshold a tad under half Vcc, 2.4 volts maybe for 5 volt parts. The newer parts can draw a *lot* of supply current if biased there, enough to glow on a thermal imager, easy to spot.
John
I sometimes wonder why they state "typical" specs. I guess it's a bit of a sanity check and gives one a decent idea about how the part performs in general, but depending upon them in a design wouldn't seem to be a very good idea IMO.
-- "Biased" there? Other than using it for some linear function or trying to speed it up by playing ECL-like games with it I can't imagine why one would want to do that in a robust logic design.
-- It\'s all about what you\'re willing to trade off. For example, if your design _must_ work, all the time, you design around worst case and make sure that the devices driving logic inputs _always_ rise above 3.5V for a high and fall below 1.5V for a low. The penalty you pay for the robustness is speed, since it takes longer to get to guaranteed switching points than it does to get to the typicals. The penalty you pay for using typicals is that you\'ll have some product fallout because the typicals aren\'t guaranteed.
Of course not.
John
Sometimes there's a huge gap between typs and guaranteed limits. A kick-ass, high-profit product can result from a prudent exploitation of that gap. The extreme case is to use a high-performance part behavior that's not specified at all.
The trick is to know when to cheat, and to only do it when the risk has a corresponding payoff.
John
We are just now testing an early batch of a new VME design that we did with all 1% resistors and lowest-grade voltage references and such. Worst-case output has a calculated tolerance of something like +-15%, and we saw no pre-calibration channels even as bad as 1% out. I think that in these days of laser trimming and mature processes, most parts are a lot better than their guaranteed specs.
John
Many I/C specifications are set high enough so as to not require testing... testing time has become a major part of the cost.
What's always amused me is that the only difference between an LM339 and an LM139 is PRICE ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
-- Being snide, John?
-- Perhaps, but the catch is, as you noted, that\'s _most_ parts, which is no different from "some product fallout".
Of course, one in a million, if he's making 200 pieces over the life of the design, may as well be zero.
good
Try throwing a on recovery time spec and see what happens to the price! In the late '70s we were paying over $50 for that same LM339.
-- Keith
a
good
s/LM339/LM356/
Sorry.
-- Keith
I was just agreeing with you.
We did a product recently that had a 3.3 volt FPGA driving some 5-volt output buffers. The logic levels were just barely legal, but the buffers were getting hot, cute white speckles on the imager. I posted about possible level-shifter circuits to fix it. We also graphed Icc versus Vin for the buffer, and got 48 mA at about +2.4 logic in.
John
good
We did leave about 16% gain headroom so we can apply per-channel cal factors, saved in eeprom at factory cal time. But using the default calibration factors that appear at first turnon, the things are almost not worth actually calibrating.
Parts are *so* good these days. And dirt cheap.
John
good
-- Unless he happens onto that one bad part or manages to latch onto 200 * however many parts he needs for his run, which came from the same lot which won't quite squeak through the window.
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