cmos circuit analysis

Apr 18, 2012 19 Replies
M

I'm trying to analyze this circuit's step response. It's a current source, with the output at the drain of M14.



This is a modification of an earlier circuit that I wanted to improve the stability of. That circuit didn't have mosfet M16, just a wire connecting M9's drain to M15's source.



It range in response to switching. It's because of huge gain in the loop that goes around M6, M11 and M14.



I'm trying to explain why M16 has a stabilizing effect.



It looks like signals go through M16 in both directions. As far as the siignal through the feedback loop I mentioned, the signal travels from M16's drain to its source. M16 acts like a low pass filter in this case, because there's no parasitic capacitance from the drain to the source; as far as the feedback signal is concerned M16 is a common base amplifier in which all the parasitic capacitances go to ground (whether to the base or to the bulk) so together with the mosfet's output resistance, it forms a low-pass filter. Is this a valid explanation?



Here's an LTSpice netlist



Version 4 SHEET 1 3160 752 WIRE 352 -256 256 -256 WIRE 368 -256 352 -256 WIRE 560 -256 368 -256 WIRE 576 -256 560 -256 WIRE 768 -256 576 -256 WIRE 784 -256 768 -256 WIRE 976 -256 784 -256 WIRE 1184 -256 976 -256 WIRE 1200 -256 1184 -256 WIRE 688 -192 496 -192 WIRE 1104 -192 688 -192 WIRE 368 -176 368 -256 WIRE 560 -176 560 -256 WIRE 432 -160 416 -160 WIRE 496 -160 496 -192 WIRE 496 -160 432 -160 WIRE 512 -160 496 -160 WIRE 768 -160 768 -256 WIRE 1184 -160 1184 -256 WIRE 688 -144 688 -192 WIRE 720 -144 688 -144 WIRE 1104 -144 1104 -192 WIRE 1136 -144 1104 -144 WIRE 352 -128 352 -256 WIRE 368 -128 352 -128 WIRE 576 -128 576 -256 WIRE 576 -128 560 -128 WIRE 784 -112 784 -256 WIRE 784 -112 768 -112 WIRE 1200 -112 1200 -256 WIRE 1200 -112 1184 -112 WIRE 432 -80 432 -160 WIRE 432 -80 368 -80 WIRE 976 -48 976 -256 WIRE 368 -32 368 -80 WIRE 368 -32 288 -32 WIRE 368 -16 368 -32 WIRE 976 0 912 0 WIRE 384 32 368 32 WIRE 1120 32 1024 32 WIRE 1184 32 1184 -64 WIRE 1184 32 1120 32 WIRE 288 64 288 -32 WIRE 320 64 288 64 WIRE 976 80 976 48 WIRE 992 128 976 128 WIRE 1184 128 1184 32 WIRE 928 160 -64 160 WIRE 1200 176 1184 176 WIRE 256 208 256 -256 WIRE 560 208 560 -80 WIRE 624 208 560 208 WIRE 768 208 768 -64 WIRE 1136 208 768 208 WIRE 560 224 560 208 WIRE 768 224 768 208 WIRE 976 224 976 176 WIRE -64 272 -64 160 WIRE 560 272 544 272 WIRE 784 272 768 272 WIRE 992 272 992 128 WIRE 992 272 976 272 WIRE 624 304 624 208 WIRE 624 304 608 304 WIRE 720 304 624 304 WIRE 368 320 368 80 WIRE 368 320 320 320 WIRE 720 336 720 304 WIRE 928 336 928 304 WIRE 928 336 720 336 WIRE 368 352 368 320 WIRE 560 352 560 320 WIRE 768 352 768 320 WIRE 976 352 976 320 WIRE 976 352 768 352 WIRE 128 384 0 384 WIRE 384 400 384 32 WIRE 384 400 368 400 WIRE 544 400 544 272 WIRE 560 400 544 400 WIRE 784 400 784 272 WIRE 784 400 768 400 WIRE 992 400 992 272 WIRE 992 400 976 400 WIRE 1120 400 1120 32 WIRE 320 432 320 320 WIRE 624 432 624 304 WIRE 624 432 608 432 WIRE 720 432 624 432 WIRE 1152 448 1120 448 WIRE 720 464 720 432 WIRE 928 464 928 432 WIRE 928 464 720 464 WIRE 128 480 128 384 WIRE 1072 480 128 480 WIRE -64 512 -64 352 WIRE 0 512 0 464 WIRE 0 512 -64 512 WIRE 256 512 256 288 WIRE 256 512 0 512 WIRE 304 512 256 512 WIRE 368 512 368 448 WIRE 368 512 304 512 WIRE 384 512 384 400 WIRE 384 512 368 512 WIRE 544 512 544 400 WIRE 544 512 384 512 WIRE 560 512 560 448 WIRE 560 512 544 512 WIRE 768 512 768 448 WIRE 768 512 560 512 WIRE 784 512 784 400 WIRE 784 512 768 512 WIRE 912 512 912 0 WIRE 912 512 784 512 WIRE 976 512 976 448 WIRE 976 512 912 512 WIRE 992 512 992 400 WIRE 992 512 976 512 WIRE 1120 512 1120 496 WIRE 1120 512 992 512 WIRE 1152 512 1152 448 WIRE 1152 512 1120 512 WIRE 1184 512 1184 224 WIRE 1184 512 1152 512 WIRE 1200 512 1200 176 WIRE 1200 512 1184 512 FLAG 304 512 0 SYMBOL pmos4 416 -80 R180 SYMATTR InstName M1 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 608 224 M0 SYMATTR InstName M2 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL voltage 256 192 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 3.3 SYMBOL nmos4 608 352 M0 SYMATTR InstName M3 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL pmos4 512 -80 M180 SYMATTR InstName M4 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 320 352 R0 SYMATTR InstName M5 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 720 224 R0 SYMATTR InstName M6 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 720 352 R0 SYMATTR InstName M7 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 928 352 R0 SYMATTR InstName M9 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL pmos4 720 -64 M180 SYMATTR InstName M10 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 1136 128 R0 SYMATTR InstName M11 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL pmos4 1136 -64 M180 SYMATTR InstName M13 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 1024 -48 M0 SYMATTR InstName M14 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL voltage -64 256 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value PULSE(0 3.3 0 10n 10n 1u 2u) SYMBOL nmos4 1072 400 R0 SYMATTR InstName M12 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 928 80 R0 SYMATTR InstName M15 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL voltage 0 368 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(3.3 0 0 10n 10n 1u 2u) SYMBOL nmos4 320 -16 R0 SYMATTR InstName M8 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 928 224 R0 SYMATTR InstName M16 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 TEXT 1296 -216 Left 2 !.MODEL CMOSN NMOS ( LEVEL = 49\n+VERSION = 3.1 TNOM = 27 TOX =



9.3E-9\n+XJ = 1.5E-7 NCH = 1.7E17 VTH0 =
0.5637114\n+K1 = 0.8583586 K2 = -0.0589493 K3 = -2.7574793\n+K3B = 1.1436533 W0 = 1E-8 NLX = 1.564468E-7\n+DVT0W = 0 DVT1W = 0 DVT2W =
0\n+DVT0 = 0.477499 DVT1 = 0.2847938 DVT2 = -0.3800695\n+U0 = 439.1496114 UA = 1.002561E-13 UB = 1.939998E-18\n+UC = 5.397035E-11 VSAT = 9.657595E4 A0 =
1.0779238\n+AGS = 0.217566 B0 = 9.363617E-7 B1 =
5E-6\n+KETA = -4.775643E-3 A1 = 1.963373E-4 A2 = 1\n+RDSW = 645.5504862 PRWG = 2.192005E-14 PRWB = -0.1195021\n+WR = 1 WINT = 9.644098E-8 LINT = 9.038343E-8\n+DWG = -1.724548E-8 DWB = -8.255139E-9 VOFF = -0.15\n+NFACTOR = 2.5 CIT = 0 CDSC = 2.4E-4\n+CDSCD = 0 CDSCB = 0 ETA0 = 1\n+ETAB = -0.0136728 DSUB = 1.1083961 PCLM =
0.9566763\n+PDIBLC1 = 2.227565E-3 PDIBLC2 = 4.305101E-3 PDIBLCB = -0.0336439\n+DROUT = 0.0499231 PSCBE1 = 3.326709E8 PSCBE2 =
4.836604E-6\n+PVAG = 0.1980844 DELTA = 0.01 RSH =
4.3\n+MOBMOD = 1 PRT = 0 UTE = -1.5\n+KT1 = -0.11 KT1L = 0 KT2 = 0.022\n+UA1 =
4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11\n+AT = 3.3E4 WL = 0 WLN = 1\n+WW = 0 WWN = 1 WWL = 0\n+LL = 0 LLN = 1 LW =
0\n+LWN = 1 LWL = 0 CAPMOD = 2\n+XPART = 0.5 CGDO = 3.66E-10 CGSO = 3.66E-10\n+CGBO =
5E-9 CJ = 8.715889E-4 PB = 0.8\n+MJ = 0.3775434 CJSW = 3.052507E-12 PBSW = 0.99\n+MJSW = 0.1 CJSWG =
1.64E-10 PBSWG = 0.99\n+MJSWG = 0.1 CF = 0 PVTH0 = 4.360674E-3\n+PRDSW = -34.2830939 PK2 = -7.347883E-3 WKETA = -0.0101632\n+LKETA = -0.0452784 ) TEXT 2216 -208 Left 2 !.MODEL CMOSP PMOS ( LEVEL = 49\n+VERSION = 3.1 TNOM = 27 TOX =
9.3E-9\n+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.5312756\n+K1 = 0.8888297 K2 = -0.1 K3 = 0\n+K3B = 4.096543 W0 = 1E-8 NLX =
1E-9\n+DVT0W = 0 DVT1W = 0 DVT2W = 0\n+DVT0 = 0.5419169 DVT1 = 0.4884952 DVT2 = -0.3\n+U0 =
142.0772561 UA = 2.074059E-9 UB = 1E-21\n+UC = -1.44971E-12 VSAT = 1.223249E5 A0 = 0.6650794\n+AGS = 0.2234747 B0 = 1.651818E-6 B1 = 5E-6\n+KETA = -0.0158936 A1 = 7.712214E-3 A2 = 0.3452462\n+RDSW =
3E3 PRWG = -0.0851397 PRWB = -0.0758646\n+WR = 1 WINT = 6.773561E-8 LINT = 1.168451E-7\n+DWG = -1.932882E-8 DWB = 1.539111E-8 VOFF = -0.0361606\n+NFACTOR = 0.8753188 CIT = 0 CDSC = 2.4E-4\n+CDSCD = 0 CDSCB = 0 ETA0 = 8.554076E-7\n+ETAB = -3.330273E-4 DSUB = 0.0540144 PCLM = 1.4696174\n+PDIBLC1 = 0.0346353 PDIBLC2 = 3.22993E-3 PDIBLCB = -0.1\n+DROUT = 0.9340703 PSCBE1 = 1E8 PSCBE2 =
5.032622E-10\n+PVAG = 0.0150037 DELTA = 0.01 RSH =
2.8\n+MOBMOD = 1 PRT = 0 UTE = -1.5\n+KT1 = -0.11 KT1L = 0 KT2 = 0.022\n+UA1 =
4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11\n+AT = 3.3E4 WL = 0 WLN = 1\n+WW = 0 WWN = 1 WWL = 0\n+LL = 0 LLN = 1 LW =
0\n+LWN = 1 LWL = 0 CAPMOD = 2\n+XPART = 0.5 CGDO = 5.6E-10 CGSO = 5.6E-10\n+CGBO = 5E-9 CJ = 9.837583E-4 PB = 0.5275652\n+MJ = 0.2031333 CJSW = 1E-14 PBSW = 0.5\n+MJSW = 0.99 CJSWG = 6.4E-11 PBSWG = 0.5\n+MJSWG = 0.99 CF = 0 PVTH0 =
5.98016E-3\n+PRDSW = 14.8598424 PK2 = 3.73981E-3 WKETA = -2.436418E-3\n+LKETA = -2.512206E-3 ) TEXT 616 56 Left 2 !.tran 10u


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J

What does "stabilizing" mean? M16 simply improves the cascode. Maybe you mean "reduced ringing"? M14 is essentially a pole-splitting capacitor.

For those attempting to follow... the .model statement (below) needs to be edited back into a single line.

...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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J

Yes, it does. But I don't feel like doing it for him.

John S

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F

Sheesh! Won't Outhouse Excuse allow you to turn off wrapping? The .models are horribly mangled. Newlines in the wrong places and far too much whitespace.

Ten minutes with a text editor to get it to load.

Basic rules for posting LTSpice circuits: No wrapping, no Greek mu, basic ASCII charset.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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J

I wrote a Macro for UltraEdit that unwraps speedily ;-)

...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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A

This has fewer transistors and less overshoot. I put the models in a .lib file:

Version 4 SHEET 1 3160 752 WIRE -144 -208 -416 -208 WIRE -128 -208 -144 -208 WIRE 112 -208 -128 -208 WIRE 128 -208 112 -208 WIRE 528 -208 128 -208 WIRE 896 -208 528 -208 WIRE 912 -208 896 -208 WIRE -416 -176 -416 -208 WIRE -128 -176 -128 -208 WIRE 112 -176 112 -208 WIRE -16 -160 -80 -160 WIRE 64 -160 -16 -160 WIRE -144 -128 -144 -208 WIRE -128 -128 -144 -128 WIRE 128 -128 128 -208 WIRE 128 -128 112 -128 WIRE -416 -64 -416 -96 WIRE 896 -64 896 -208 WIRE -128 -48 -128 -80 WIRE -16 -48 -16 -160 WIRE -16 -48 -128 -48 WIRE 848 -48 -16 -48 WIRE 912 -16 912 -208 WIRE 912 -16 896 -16 WIRE 528 16 528 -208 WIRE -128 80 -128 -48 WIRE -128 80 -208 80 WIRE -128 96 -128 80 WIRE 896 96 896 32 WIRE 896 96 576 96 WIRE 112 128 112 -80 WIRE 192 128 112 128 WIRE 112 160 112 128 WIRE 896 160 896 96 WIRE -208 176 -208 80 WIRE -176 176 -208 176 WIRE -128 240 -128 192 WIRE -128 240 -208 240 WIRE 192 240 192 128 WIRE 192 240 160 240 WIRE 528 240 528 112 WIRE 528 240 368 240 WIRE 848 240 736 240 WIRE -128 272 -128 240 WIRE 112 272 112 256 WIRE 368 272 368 240 WIRE 528 272 528 240 WIRE 736 272 736 240 WIRE -208 352 -208 240 WIRE -176 352 -208 352 WIRE 192 352 192 240 WIRE 192 352 160 352 WIRE 288 352 192 352 WIRE 320 352 288 352 WIRE 480 352 464 352 WIRE -128 384 -128 368 WIRE 112 384 112 368 WIRE 368 384 368 368 WIRE 528 384 528 368 WIRE 736 384 736 352 WIRE 896 384 896 256 WIRE 288 432 288 352 WIRE 464 432 464 352 WIRE 464 432 288 432 FLAG -128 144 0 FLAG -128 320 0 FLAG 112 320 0 FLAG 112 208 0 FLAG 368 320 0 FLAG 528 320 0 FLAG 896 208 0 FLAG 528 64 0 FLAG -416 -64 0 FLAG -128 384 0 FLAG 112 384 0 FLAG 368 384 0 FLAG 528 384 0 FLAG 896 384 0 FLAG 736 384 0 SYMBOL pmos4 -80 -80 R180 SYMATTR InstName M1 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 160 160 M0 SYMATTR InstName M2 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL voltage -416 -192 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 3.3 SYMBOL nmos4 160 272 M0 SYMATTR InstName M3 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL pmos4 64 -80 M180 SYMATTR InstName M4 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 -176 272 R0 SYMATTR InstName M5 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 320 272 R0 SYMATTR InstName M7 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 480 272 R0 SYMATTR InstName M9 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL pmos4 848 32 M180 SYMATTR InstName M13 SYMATTR Value CMOSP SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 576 16 M0 SYMATTR InstName M14 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL nmos4 848 160 R0 SYMATTR InstName M12 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 SYMBOL voltage 736 256 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V3 SYMATTR Value PULSE(3.3 0 0 10n 10n 1u 2u) SYMBOL nmos4 -176 96 R0 SYMATTR InstName M8 SYMATTR Value CMOSN SYMATTR Value2 l=1u w=100u m=1 TEXT 168 40 Left 2 !.tran 10u TEXT 168 72 Left 2 !.include CMOS.lib

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F

Which is where?

-- "For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)

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J

[snip]

Not the way us PLL guys would do it, but...

Lack of wrap in the models... fixed. Tabs -> spaces Killed lots of white space Notation changed to allow running on PSpice and others:

  • C:\Program Files\LTC\SwCADIII\examples\SED\ChargePump_MichaelRobinson\ChargePump_AndrewHolme.asc M1 N002 N002 N001 N001 CMOSP l=1u w=100u m=1 M2 N004 N004 N008 0 CMOSN l=1u w=100u m=1 V1 N001 0 3.3 M3 N008 N004 0 0 CMOSN l=1u w=100u m=1 M4 N004 N002 N001 N001 CMOSP l=1u w=100u m=1 M5 N005 N005 0 0 CMOSN l=1u w=100u m=1 M7 N006 N004 0 0 CMOSN l=1u w=100u m=1 M9 N006 N004 0 0 CMOSN l=1u w=100u m=1 M13 N003 N002 N001 N001 CMOSP l=1u w=100u m=1 M14 N001 N003 N006 0 CMOSN l=1u w=100u m=1 M12 N003 N007 0 0 CMOSN l=1u w=100u m=1 V3 N007 0 PULSE(3.3 0 0 10n 10n 1u 2u) M8 N002 N002 N005 0 CMOSN l=1u w=100u m=1
*.model NMOS NMOS *.model PMOS PMOS *.lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos *.tran 10u *.include CMOS.lib *.backanno *.end

.MODEL CMOSN NMOS ( LEVEL= 7

+VERSION = 3.1 TNOM= 27 TOX = 9.3E-9 +XJ = 1.5E-7 NCH = 1.7E17 VTH0= 0.5637114 +K1 = 0.8583586 K2 = -0.0589493 K3 = -2.7574793 +K3B = 1.1436533 W0 = 1E-8 NLX = 1.564468E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0= 0.477499DVT1= 0.2847938 DVT2= -0.3800695 +U0 = 439.1496114UA = 1.002561E-13 UB = 1.939998E-18 +UC = 5.397035E-11 VSAT= 9.657595E4 A0 = 1.0779238 +AGS = 0.217566B0 = 9.363617E-7 B1 = 5E-6 +KETA= -4.775643E-3 A1 = 1.963373E-4 A2 = 1 +RDSW = 645.5504862PRWG= 2.192005E-14 PRWB= -0.1195021 +WR = 1 WINT= 9.644098E-8 LINT= 9.038343E-8 +DWG = -1.724548E-8 DWB = -8.255139E-9 VOFF= -0.15 +NFACTOR = 2.5 CIT = 0 CDSC= 2.4E-4 +CDSCD = 0 CDSCB = 0 ETA0= 1 +ETAB= -0.0136728 DSUB= 1.1083961 PCLM= 0.9566763 +PDIBLC1 = 2.227565E-3 PDIBLC2 = 4.305101E-3 PDIBLCB = -0.0336439 +DROUT = 0.0499231 PSCBE1 = 3.326709E8 PSCBE2 = 4.836604E-6 +PVAG= 0.1980844 DELTA = 0.01RSH = 4.3 +MOBMOD = 1 PRT = 0 UTE = -1.5 +KT1 = -0.11 KT1L= 0 KT2 = 0.022 +UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11 +AT = 3.3E4 WL = 0 WLN = 1 +WW = 0 WWN = 1 WWL = 0 +LL = 0 LLN = 1 LW = 0 +LWN = 1 LWL = 0 CAPMOD = 2 +XPART = 0.5 CGDO= 3.66E-10CGSO= 3.66E-10 +CGBO= 5E-9 CJ = 8.715889E-4 PB = 0.8 +MJ = 0.3775434 CJSW= 3.052507E-12 PBSW= 0.99 +MJSW= 0.1 CJSWG = 1.64E-10PBSWG = 0.99 +MJSWG = 0.1 CF = 0 PVTH0 = 4.360674E-3 +PRDSW = -34.2830939 PK2 = -7.347883E-3 WKETA = -0.0101632 +LKETA = -0.0452784 )

.MODEL CMOSP PMOS ( LEVEL= 7

+VERSION = 3.1 TNOM= 27TOX = 9.3E-9 +XJ = 1.5E-7 NCH = 1.7E17 VTH0= -0.5312756 +K1 = 0.8888297 K2 = -0.1K3 = 0 +K3B = 4.096543W0 = 1E-8 NLX = 1E-9 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.5419169 DVT1= 0.4884952 DVT2= -0.3 +U0 = 142.0772561UA = 2.074059E-9 UB = 1E-21 +UC = -1.44971E-12 VSAT= 1.223249E5 A0 = 0.6650794 +AGS = 0.2234747 B0 = 1.651818E-6 B1 = 5E-6 +KETA= -0.0158936 A1 = 7.712214E-3 A2 = 0.3452462 +RDSW= 3E3 PRWG= -0.0851397 PRWB= -0.0758646 +WR = 1 WINT= 6.773561E-8 LINT= 1.168451E-7 +DWG = -1.932882E-8 DWB = 1.539111E-8 VOFF= -0.0361606 +NFACTOR = 0.8753188 CIT = 0 CDSC= 2.4E-4 +CDSCD = 0 CDSCB = 0 ETA0= 8.554076E-7 +ETAB= -3.330273E-4 DSUB= 0.0540144 PCLM= 1.4696174 +PDIBLC1 = 0.0346353 PDIBLC2 = 3.22993E-3 PDIBLCB = -0.1 +DROUT = 0.9340703 PSCBE1 = 1E8 PSCBE2 = 5.032622E-10 +PVAG= 0.0150037 DELTA = 0.01RSH = 2.8 +MOBMOD = 1 PRT = 0 UTE = -1.5 +KT1 = -0.11 KT1L= 0 KT2 = 0.022 +UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11 +AT = 3.3E4 WL = 0 WLN = 1 +WW = 0 WWN = 1 WWL = 0 +LL = 0 LLN = 1 LW = 0 +LWN = 1 LWL = 0 CAPMOD = 2 +XPART = 0.5 CGDO= 5.6E-10 CGSO= 5.6E-10 +CGBO= 5E-9 CJ = 9.837583E-4 PB = 0.5275652 +MJ = 0.2031333 CJSW = 1E-14 PBSW= 0.5 +MJSW= 0.99CJSWG = 6.4E-11 PBSWG = 0.5 +MJSWG = 0.99CF = 0 PVTH0 = 5.98016E-3 +PRDSW = 14.8598424 PK2 = 3.73981E-3 WKETA = -2.436418E +LKETA = -2.512206E-3)

.end ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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F

Thanks. There's still a lot of spare whitespace there. This is what I cleaned out of Michael's original posting. Looks identical but more manageable:

Quite what "level 49" is, I don't know, unless it's "Level 7 squared" ;-)

.MODEL CMOSN NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 9.3E-9 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.5637114 +K1 = 0.8583586 K2 = -0.0589493 K3 = -2.7574793 +K3B = 1.1436533 W0 = 1E-8 NLX = 1.564468E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.477499 DVT1 = 0.2847938 DVT2 = -0.3800695 +U0 = 439.1496114 UA = 1.002561E-13 UB = 1.939998E-18 +UC = 5.397035E-11 VSAT = 9.657595E4 A0 = 1.0779238 +AGS = 0.217566 B0 = 9.363617E-7 B1 = 5E-6 +KETA = -4.775643E-3 A1 = 1.963373E-4 A2 = 1 +RDSW = 645.5504862 PRWG = 2.192005E-14 PRWB = -0.1195021 +WR = 1 WINT = 9.644098E-8 LINT = 9.038343E-8 +DWG = -1.724548E-8 DWB = -8.255139E-9 VOFF = -0.15 +NFACTOR = 2.5 CIT = 0 CDSC = 2.4E-4 +CDSCD = 0 CDSCB = 0 ETA0 = 1 +ETAB = -0.0136728 DSUB = 1.1083961 PCLM = 0.9566763 +PDIBLC1 = 2.227565E-3 PDIBLC2 = 4.305101E-3 PDIBLCB = -0.0336439 +DROUT = 0.0499231 PSCBE1 = 3.326709E8 PSCBE2 = 4.836604E-6 +PVAG = 0.1980844 DELTA = 0.01 RSH = 4.3 +MOBMOD = 1 PRT = 0 UTE = -1.5 +KT1 = -0.11 KT1L = 0 KT2 = 0.022 +UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11 +AT = 3.3E4 WL = 0 WLN = 1 +WW = 0 WWN = 1 WWL = 0 +LL = 0 LLN = 1 LW = 0 +LWN = 1 LWL = 0 CAPMOD = 2 +XPART = 0.5 CGDO = 3.66E-10 CGSO = 3.66E-10 +CGBO = 5E-9 CJ = 8.715889E-4 PB = 0.8 +MJ = 0.3775434 CJSW = 3.052507E-12 PBSW = 0.99 +MJSW = 0.1 CJSWG = 1.64E-10 PBSWG = 0.99 +MJSWG = 0.1 CF = 0 PVTH0 = 4.360674E-3 +PRDSW = -34.2830939 PK2 = -7.347883E-3 WKETA = -0.0101632 +LKETA = -0.0452784 )

.MODEL CMOSP PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 9.3E-9 +XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.5312756 +K1 = 0.8888297 K2 = -0.1 K3 = 0 +K3B = 4.096543 W0 = 1E-8 NLX = 1E-9 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.5419169 DVT1 = 0.4884952 DVT2 = -0.3 +U0 = 142.0772561 UA = 2.074059E-9 UB = 1E-21 +UC = -1.44971E-12 VSAT = 1.223249E5 A0 = 0.6650794 +AGS = 0.2234747 B0 = 1.651818E-6 B1 = 5E-6 +KETA = -0.0158936 A1 = 7.712214E-3 A2 = 0.3452462 +RDSW = 3E3 PRWG = -0.0851397 PRWB = -0.0758646 +WR = 1 WINT = 6.773561E-8 LINT = 1.168451E-7 +DWG = -1.932882E-8 DWB = 1.539111E-8 VOFF = -0.0361606 +NFACTOR = 0.8753188 CIT = 0 CDSC = 2.4E-4 +CDSCD = 0 CDSCB = 0 ETA0 = 8.554076E-7 +ETAB = -3.330273E-4 DSUB = 0.0540144 PCLM = 1.4696174 +PDIBLC1 = 0.0346353 PDIBLC2 = 3.22993E-3 PDIBLCB = -0.1 +DROUT = 0.9340703 PSCBE1 = 1E8 PSCBE2 = 5.032622E-10 +PVAG = 0.0150037 DELTA = 0.01 RSH = 2.8 +MOBMOD = 1 PRT = 0 UTE = -1.5 +KT1 = -0.11 KT1L = 0 KT2 = 0.022 +UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11 +AT = 3.3E4 WL = 0 WLN = 1 +WW = 0 WWN = 1 WWL = 0 +LL = 0 LLN = 1 LW = 0 +LWN = 1 LWL = 0 CAPMOD = 2 +XPART = 0.5 CGDO = 5.6E-10 CGSO = 5.6E-10 +CGBO = 5E-9 CJ = 9.837583E-4 PB = 0.5275652 +MJ = 0.2031333 CJSW = 1E-14 PBSW = 0.5 +MJSW = 0.99 CJSWG = 6.4E-11 PBSWG = 0.5 +MJSWG = 0.99 CF = 0 PVTH0 = 5.98016E-3 +PRDSW = 14.8598424 PK2 = 3.73981E-3 WKETA = -2.436418E-3 +LKETA = -2.512206E-3 )
"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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J

I fixed it all in...

Message-ID:

Level=49 is HSpice's number for PSpice level=7. I don't know what LTspice calls it.

[snip]

...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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F

IOW, PSpice = sqrt(HSpice)?

Same as 25.806976 = The Root Of All Evil ;-)

Level 7 isn't in the manual. 4 is BSIM, 5 is BSIM2, 6 is MOS6 (Sakurai & Newton), 8 is BSIM3.3.0, 9 is BSIMSOI 3.2, 12 is EKV2.6, 14 is BSIM 4.6.1.

7 (BSIM 3.2 ??) doesn't appear in the manual. It appears to work, though.
"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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J

In PSpice....

LEVEL=1 Shichman-Hodges model LEVEL=2 geometry-based, analytic model LEVEL=3 semi-empirical, short-channel model LEVEL=4 BSIM model LEVEL=5 EKV model version 2.6 LEVEL=6 BSIM3 model version 2.0 LEVEL=7 BSIM3 model version 3.2

I think LTspice recognizes quite a few of PSpice conventions. I know I've simply pasted a PSpice netlist into LTspice, and it runs just fine.

LTspice is a fine simulator. I just wish its schematic-entry was more user friendly. And its post-processor more professional looking ;-) ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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J

It's plenty friendly with this here user. I like it. It's far less clickety than what I remember of Pspice. (Which I abandoned years ago in favour of LTspice.)

I agree about the post-processor. In particular, the choice of vertical scale divisions never seems to agree with me and it can't be made to respect *my* settings from one run to the next.

Jeroen Belleman

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I'd go along with that.

That's a nuisance. Every run resets the axes to what *it* thinks. Old-fashioned Berkeley 3f4 could be made to format axes the same every run. That used gnuplot, AFAIR.

I wish LTSpice could do polar and Smith plots, and PZ analysis, like 3f4.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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J

I think _all_ of them are too "clickety", and too hung up on pull-down menus. I'm a Macro Express nut... I have developed hot key macros for every function PSpice didn't provide a hot key for.

Between Probe and Acrobat I can massage everything into "pretty" enough to impress the customer ;-) ...Jim Thompson

| James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
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J

But LTspice *will* do polar plots. I've done it, but I'll have to look into this again to see how I did it. It's not something I do very often. The last time, if I remember well, was a polar plot of the input impedance of an approximation of a passive constant input impedance low-pass filter. My, my, that was seven years ago. How time flies.

As for Smith plots, you can get the shape of the curves with a bi-linear transform or by inserting a bridge in your circuit somewhere. The axes remain Cartesian, alas. I agree it's nothing like the convenience of a VNA.

Jeroen Belleman

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J

LTspice will make polar plots of complex variables by left-clicking the left vertical axis and selecting Representation->Nyquist. Is that what you wanted?

Jeroen Belleman

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I've done it by importing LTSpice rawfiles into 3f4 nutmeg. Needs ASCII rawfiles, they get huge.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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F

No. Nyquist axes are still Cartesian.

X=real, Y=imaginary.

What I'd like is "proper" polar. R vs Theta. Like Berkeley Spice does.

"For a successful technology, reality must take precedence over public relations, for nature cannot be fooled." (Richard Feynman)
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