CMOS logic level range

Mar 08, 2007 40 Replies

a

good

We're talking more about situations where the variations tend to cancel out, which rules out the "parts from one lot" causing it all by itself. So, you'd have to have n lots, different parts, from different factories, each lot which would unusually bad, in the worst-case direction, against astronomical odds.

Then you'd get to do a bit of rework when the board fails to calibrate in... but that would be *far* likely to happen from some other reason. It might even be an indicator that the parts are not reliable if they are so far off. If you double the range of calibration to take care of the sparse possibly outlying points you may be penalizing the performance or stability of every unit a bit just to eliminate that last little bit of risk (say, due to the resolution and stability of digital calibration or the long-term or temeperature stability of an analog trimpot setting).

I'm not saying it's always the right thing to do, just that it may be worth evaluating risk vs. reward. Generally, I've not had problems from the design risks which I've faced head-on and evaluated. It's that occasional thing that comes out of left field*...

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Best regards, Spehro Pefhany

"it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com

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