cmos-logic -- low dynamic power dissipation

What i really like on this ultra low voltage stuff is how to interface to normal logic. This is where the part count goes up.

Rene

Actually, you raise a point, which is that the dynamic power-dissipation capacitance is measured with fast-risetime full-logic-swing test signals applied to the gate. Obviously a Schmitt-trigger gate (or any gate) will draw much more current when operating with a low-voltage slow-risetime input. You may be able to infer an improved performance for these parts under such a conditions, but you won't be able to come up with an actual number from the datasheet specs.

In general, bipolar transistors usually beat out CMOS for ultra low power oscillators.

Doesn't the Schmitt-trigger gate draw extra current because its input is operating near the threshold? (ok, the threshold keeps moving, but I thought that each time you approach it, the supply draws more current.) I wonder if there is a way around this. If you could run the supply at less than the sum of the N-ch and P-ch threshold voltages, that would be a start, but then I think Schmitt triggers don't work under that condition.

Chris

I measure 700uA @ Vdd = +4V for this fellow (below), and about half that at Vdd = +3V.

' R1 68k ' ___ D1 ' .-------|___|-----|

Those numbers are in line with some of the datasheet graphs for 74hc132 current consumption for linear inputs, such as those in the Philips datasheet. We can speculate how TI's new 74aup parts might fare by comparison. Their 4pF power-dissipation capacitance is 3 to 8 times lower than the power-dissipation capacitance specs for various manufacturer's 74hc132 parts, which is one comparison factor, and they can be operated at much lower voltages, which is another.

Tapered turn-on/off output stages. First developed for ground bounce reasons.

...Jim Thompson

Please give us a detailed tutorial. Thanks in advance.

Pretty trivial, once you see it...

Imagine an RC delay line with an MOS gate at each tap. Size the delays and device sizes appropriately and you can create just about any shape of rise and fall time, with appropriate reduction in current spike... my favorite, of course, is TANH ;-)

...Jim Thompson

Sure, but a schmitt trigger's feedback will insure that it's in the linear range for a short period. CMOS conducts massively in the linear/crossover/shoot-through region. Once the output snaps it should draw very little current. A schmitt trigger should make a slow input far less of a problem (the gain thing).

Not quite. After the output snaps the output stage will draw very little current, but the input stage, which was the current-drawing offender to begin with, still draws substantial current, and it will continue to do so until the *input voltage* moves well away from the trigger voltage. The Philips datasheet shows this effect clearly, especially if the part is operated at 5V. Lower-voltage parts do better, but the 74LV132 still shows this effect when operated at 3V.

It would be interesting to see such a plot for TI's new 74aup1G14.