Can I "reset" an AD9901?

I am using an Analog-devices AD9901 to lock the phase between two 1-MHz signals.

The problem is that the state of the flip-flops is random at power on. Since the phase between my 2 signals varies in a limited phase domain, sometimes my output signal remains stuck at either limit of its range. Of course a 2*pi phase variation would solve my problem. I cheat by disabling either input signal for a brief moment.

Is there any way to force the statusses of both flip-flops on request?

Regards,

Reply to
Jean-Pierre Coulon
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We use AD9901 and haven't seen that problem. Might you actually have a pull-lock range problem?

It's expensive for a 1 MHz loop.

Reply to
jlarkin

I gather it's locking two sources using a variable delay (or phase shifter) rather than a VCO.

There are two nulls per cycle, one of which is unstable. With a PLL, there's always a stable null to be found--if the initial phase is pushing you away from an unstable one, the next one it finds will be stable.

However, if you're using a phase shifter with a limited range, then if you fetch up on the wrong side of the unstable null, the loop will rail and stay railed.

Lo these many years ago (1985ish), I built a successive-approximation phase digitizer. To avoid this exact problem, I tested the phase detector output at the conversion pulse, set a flipflop, and used that plus an XOR gate to make sure the SAR was shooting for the stable null.

Cheers

Phil Hobbs

Reply to
Phil Hobbs

Yeah, a delay loop would be different. In a frequency loop, the 9901 should drive towards lock if it possibly can.

A single d-flop would be a good delta-t detector for a time lock loop. We've done that to a few 10s of fs.

Reply to
jlarkin

The AD9901 is a truly horrible phase detector. The concept starts with a deep misunderstanding of the reason for deadband near the center of the transfer curve.

Deadband is not produced in the digital portion of the phase detector. It is produced in the following analog section when the propagation delay through one path is slower than the delay through the other path.

An example is shown in Jim Thompson's MC4044 phase/frequency detector. The pullup path is a complicated discrete inverter, and the pulldown path is a simple diode. The pullup path is much slower than the pulldown path, and the detector produces no output for late samples near the center of the transfer curve.

This is shown in the LTspice file DEADBAND.ASC in the following link:

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The companion file, FASTDIOD.ASC shows the pullup path replaced by a diode, the same as the pulldown path. The pullup and pulldown paths are both equal and very fast, and the phase detector output is now continuous through zero.

You can duplicate this performance at low frequencies by using ordinary CMOS 74AC74 and 74AC00 chips. For higher frequencies, MECL ECLINPS ic's will work. There are also a number of commerial chips, but beware of AD9901 clones. Stay away from any ones that feature XOR operation to eliminate deadband. They have terrible ripple and drift.

Your problem is trying to synchronize two asynchronous signals. Since the phase between them is random, the phase/frequency detector can start in any phase. The loop can go through a severe transient until the phases line up, when the loop will settle down and lock. One way around this problem is to start the oscillators in phase, but you also have to be careful to reset both d-flops in the phase detector so they also start in the same phase.

This can get tricky, as shown in my 1971 Memorex patent. This was the data recovery channel for the IBM-3330 compatible disc drive that use MFM data encoding. The channel had a very brief time at the beginning of the sector to identify the synchronisation area, start the voltage-controlled oscillator in the correct phase, and release the phase/frequency detector in the correct phase to decode the incoming data. It also had to have zero deadband and produce minimum jitter while following large phase errors from the incoming data.

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Reply to
Mike Monett

Indeed if I enter a test signal at 1 MHz and the other at 1.0000001 MHz I see a ramp for 10 seconds, a rest at the rail value for 10 seconds and this succession again.

In the real world I have a phase shifter with a range of about -120:120 deg.

Perhaps I should design my own AD9901 with circuits and reset both flip-flops. :-)

Bye,

Reply to
Jean-Pierre Coulon

Am 08.03.22 um 19:02 schrieb Mike Monett:

No. The AD9901 is good. I had excellent results with it.

What are you talking about? There is no analog section in the AD9901.

I even have a compilable VHDL version of it that fits into a tiny corner of a Xilinx Coolrunner II.

What has the Helgoland island to do with all of this?

I have the impression that you mix something with the CD4046 and its ilk. That has the problem that the charge pumps deliver no gain Kp when there is no phase error. That can be mostly healed with a 1 Meg bleed resistor.

And even there, the 9046 has corrected that for good.

I would really like the 9046 if I could switch off its VCO. I do not want an unneeded frequency on my board.

Gerhard

Reply to
Gerhard Hoffmann

??? Do you understand LTspice?

Reply to
Mike Monett

FYI, NTP (Network Time Protocol) solves this problem using a combination of a PLL (phase lock loop) and a FLL (frequency lock loop), implemented in software. The loop time constant is something like 50 minutes.

Joe Gwinn

Reply to
Joe Gwinn

A single flop is all you may need. Measure early/late bang-bang.

But if you can only shift 120 degrees and need 180, that's a problem.

If the sources can indeed be different frequencies, the phase shifter has to wrap forever.

Reply to
John Larkin

Yeah, I've been meaning to try out one of those 10EP dflops that you like.

Cheers

Phil Hobbs

Reply to
Phil Hobbs

I did an interesting laser locker about 10 years ago. It used both current- and temperature-tuning of a 1.55 um DFB diode laser. The most interesting point was that there was only one loop running both--the temperature-tuning did the initial lock acquisition using a slow triangular sweep, and then when the current-tuning signal came off the peg, it was so much faster that it took over the loop completely, leaving the temperature tuning to keep the bias current in the centre of its range.

It used R-T locking, which is probably my second best trick.

Cheers

Phil Hobbs

Reply to
Phil Hobbs

One approach is to look for the output going to the rail, and invert the phase of one of the signals (using a gate or resetting some dflop).

Cheers

Phil Hobbs

Reply to
Phil Hobbs

Pin 5 is the oscillator inhibit input; that disables one of the phase comparators, too.

Floating pins 11 and 12 should turn the VCO off; ground or pullup on pins 6 and 7 should, too.

Reply to
whit3rd

That's pretty cute.

I think that most Rubidium vapor-cell secondary standards do much the same thing - they sweep slowly in frequency (~200 Hz p-p) until they see a dip in the optical output, then stop sweeping and converge to lock on that dip.

R-T Locking?

Joe Gwinn

Reply to
Joe Gwinn

About the fastest non-Russian flop around is probably NB7V52. We walked the clock and data edges across one another:

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That jitter includes the circuits that generated the time sweeps.

D-flop bang-bang discriminators rock, but people seem to avoid them.

Hittite has some fast logic too, at crazy prices.

Reply to
John Larkin

The OP's problem could be explained by the +-120 phase shifter, and the divide-by-2 flops in the AD9901.

If he needs 170 degrees of shift to lock, a random restart of the flops might turn that into 10 degrees.

Reply to
John Larkin

The problem is discussed on ages 8 and 9 of the data sheet for the Philips/NXP 9046 version of the 4046, which was designed to avoid it

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It's nowhere near as fast as the AD9901. If you force the phase detector to stabilise at a point where detected pulse is wider than the switching times, you avoid the problem, as Phil Hobbs has pointed out here. Doing this can create other problems

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Reply to
Anthony William Sloman

Am 08.03.22 um 22:46 schrieb whit3rd:

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From the data sheet:

The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input (pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to minimize standby power consumption

But you are right, the block diagram contradicts this. Unfortunately, the remaining phase detector is just the XOR gate, not the interesting one. That could be cheaper with a LVC-86 gate.

R1, R2 is specified as 3K-300K, C1 > 40 pF Leaving them out does not guarantee that the VCO is dead, only that it does not behave.

But one could try it. Asking Nexperia will probably lead to nothing.

Ah, Unobtainium @ DK, some @ Rochester.

Thanks! Gerhard

Reply to
Gerhard Hoffmann

Methinks yes, I do.

And generic Spice also from the inside. Back then(R) we had to program all the interesting algorithms ourselves before we were given the 2G6 sources. Later I ported V3 to Interactive Unix on a 386.

Did you even notice that we were talking about AD9901 and not about your MC4044?

Hint: They could not be more different.

Reply to
Gerhard Hoffmann

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