Hello,
In a current FPGA-based design, I have a sub-block whose synchronous outputs drive some logic such as counters & flip-flops(external to the sub-block but internal to the FPGA). The current design has the sub-block synchronously enabled when it needs to be used and synchronously disabled when it does not need to be used.
When the block is de-selected (going from enabled to disabled), I would like the sub-block's flip-flops to be reset, so the next time the block is enabled, the outputs are in a known state.
My question:
Is it safe to use a synchronous reset signal which is high for one system clock cycle to drive the async reset on the flip-flops of my sub-block?
Note: The sub-block flip-flops are synchronously disabled before being reset by the synchronous reset signal, so I am not creating a setup/hold time problem with the sub-block FFs.
My real concern is about violating the setup & hold time on the flip-flops the sub-block drives. My thinking is that even though the reset signal is synchronous, the sync. reset signal will probably not be distributed via a low-skew line (aka global signal) and I could potentially have a far sub-block flip-flop not reset by the time the clock comes around, and thus I clober a flip-flop which is driven by a s-b FF.
If driving the async. reset on the FFs is a bad idea, my other approach was to take each DFF of the sub-block and update it to include a 2-input AND gate on the input. One input to the AND2 gets the original D-input signal while the second input gets a NOTed SCLR(active high), so I create a synchronous clearable DFF.
I would appreciate comments, suggestions, etc.
Jay