XOR pd's have low gain, volts per second. The virtue of the 9901 is that it can run at 200 MHz, and that might avoid dividing down into a slower phase detector.
Of course, you can run an ecl xor or a diode mixer at GHz's, but you need to get into lock range, which the 9901 does for you.
We've done dpflop phase detectors in PLLs at 155 MHz. The gain is basically infinite. We run the loop super wideband to achieve lock, then narrow down after we have lock, to get better phase noise.
One can also do dumb things in an fpga, like comparing counters, to get into lock, then cut over to some high-gain phase detector.
You don't need the delay to be tunable, though--you can put in some integral number of cycles' worth of extra path delay in one arm, and just change the rep rate of the pulses. If the jitter in the clock is too large for that to work, the clock probably has other problems. (If the duty cycle is known to be stable enough, you can use half the delay.)
The delay discriminator thing is nearly totally insensitive to low-frequency jitter, which is where most of it lives.
That's where the RF guys come in. A 300 MHz sinusoidal signal with 100 fs of jitter between adjacent pulses would have a phase uncertainty of
<dPhi> = 2 pi * 100 fs * 300 MHz = 0.0002 radian.
in the corresponding bandwidth (which we'll get to).
That's a total phase noise power of -74 dBc. The sensitive bandwidth peaks at 150 MHz with a cosine squared characteristic, so its bandwidth is effectively 150 MHz. If we can get to the Johnson noise limit with a signal of 0 dBm, even in the full 150 MHz Nyquist interval, that's
CNR = -174.5 dBm/Hz + 10 log (150e6) = -92.0 dBc,
well within spec. With a decent sine wave source, it should be no problem to do that with a filter of, say, 10 MHz bandwidth.
A power amp running into a Schottky diode clipper should square the waveform up nicely, so a reasonably vanilla RF synthesizer should work fine, I should think.
One could check that by building two of them, one having the delay in the clock and the other in the data--cross-correlating the results would be a reasonable measure of the clock's jitter contribution vs. the dflop's.
Anyway, that's one applied physicist's approach. Fun problem, for sure--it sure isn't the sort of regime one would normally expect to be in!
Of course, since the dflop and a 4046-style PFD both want to lock at zero degrees, you could just sum the two and let the dflop keep the loop in the centre of the deadband, where the PFD doesn't do anything.
The correlation measurement ought to do that. Even at 0 dBm, the filter / amp / clipper ought to get down to 12 fs or so--it's 18 dB quieter than it needs to be.
With the filter placed after a power amp (maybe with a 3 dB pad between filter and clipper), the noise floor will still be near the Johnson noise but the signal amplitude will be much larger.
So starting with +24 dBm, filtering, and then clipping should reach 1 fs RMS.
Maybe Gerhard or even Joerg will chime in with a sanity check of my numbers, but I think they're reasonable, and the method is sure convenient to use--the delay is self-calibrating, so the phase shift vs. frequency is super well defined.
I was wondering whether anyone bothers to ovenize teflon boards, for example with some SMT power resistors and thermistors scattered between the RF stuff or on the back side of the board. You could stabilise each region of the board at say 50 C, so the phase shifts might stay put a bit better (after a brief warm-up). I had thought that might be worth doing also for semi-rigid cabling inside test equipment.
I'm sure somebody has done this. Typical OCXO oven temperature is like 80 C, well above the Teflon knee, so Teflon may be well enough behaved up there.
MC9046 was a typo copied from Gerhard. It should be MC4046.
The AD9901 is 0.2568V/Rad. Fig 7, Gain/Phase Plot, Page 6,
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Doesn't matter. You can make it up in the amplifier. However, the penalty with an XOR is the horrible ripple output when locked. The AD9901 swings from VOH to VOL, or about 2V p-p. This creates unwanted spurs in the oscillator output.
The AD9901 is a very old chip. The datasheet is copyrighted 1999. It claims to use ecl, but the output is collector driven instead of emitter follower. This is one reason why the performance is so poor.
It already divides by two to drive the XOR. The linear region starts compressing at 50 MHz. The device is almost useless at 200 MHz. See Gain/Phase plot, above.
You can make your own phase/frequency detector with 100EP chips that may run up to 1 GHz. The Hittite HMC series of 13 GHz chips can run faster.
The beauty of a dual d-flop phase/frequency detector is guaranteed frequency lock when in range, and zero ripple output when locked.
If you are running a dual d-flop pfd, I don't see why you need to run at high bandwidth to achieve lock. The dual-d already does that for you.
The problem with switching gain after lock is now the loop has to correct the offsets caused by switching while in slow mode. This can take a long time.
If you need to synthesize different frequencies, modern synthesizer chips such as the TI LMX2820 go up to 22.6 GHz, include the VCO and integer- boundary spur (IBS) removal, and offer very low PLL phase noise of -236 dBc/Hz:
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ADI has a large variety of Fractional-N synthesizers that go up to 32 GHz:
As above, when you switch from one mode to another, you have to correct for unavoidable phase errors. These will usually occur in the slow mode, which can take a long time and is difficult to define. I had this problem in my Memorex patent of 1971, where I had to start a vco and phase detector in phase with the incoming data in the minimum amount of time and with the minimum phase error. See
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The approach shown in this patent not only solved the problem, but it also led to another invention that changed the magnetic recording industry and led to the incredible orders of magnitude increase in disk drive performance since then. Many brilliant individuals have made significant contributions to the technology, but they relied on this invention to tell them the correct path.
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