timing-sensitive
main(). That
timing.
isn't very
CPU
Or, depending on the processor, .3 to 10. Then there are the processors with decoupled/asynchronous I/O... Super-scalars...
Again, you mentioned NOP timing, which is just nuts with a modern CPU architecture.
Yes. My first "benchmark" attempt came up like this:
Double Precision: 0.270us / 32.406 cycles /multiply 0.238us / 28.652 cycles /add 0.234us / 28.152 cycles /divide Single Precision: 0.181us / 21.723 cycles /multiply 0.134us / 16.101 cycles /add 0.130us / 15.602 cycles / divide
Unfortunately I posted it before I realised my dumb benchmarking loop was driving some of the variables to zero. So the FP routines could and did exit early!
timing-sensitive
main(). That
timing.
yet--I'm
isn't very
shorter
Of
much
is
speed
like CPU
ISR,
it's
like
I dug into this a bit more, and discovered that NXP claims a fixed
12-cycle interrupt latency, so it looks as though they solved this problem already. STM32F and L both say "maximum 12 cycles".So obviously PICs still rule for timing. ;)
Cheers
Phil Hobbs
timing-sensitive
main(). That
timing.
yet--I'm
isn't very
shorter
I'm
Of
much
is
speed
like CPU
ISR,
it's
like
The LPC3250 has *one* interrupt vector; the front-end of the ISR has to figure out whodunnit. This is PDP-8 technology.
timing-sensitive
main(). That
timing.
yet--I'm
isn't very
shorter
Of
much
is
speed
like CPU
ISR,
it's
like
My early stuff has started to get reinvented too. ;)
Cheers
Phil Hobbs
timing-sensitive
main(). That
timing.
yet--I'm
isn't very
shorter
I'm
Of
much
is
speed
like CPU
ISR,
it's
like
Doesn't do anything, but it's sure consistent! ;-)
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