AoE III price lowered another $10

On Thu, 04 Jun 2015 07:52:51 -0700, Jim Thompson Gave us:

It is at least 30 year old, "old hat" stuff.

Am 04.06.2015 um 16:57 schrieb Spehro Pefhany:

My sources I was talking about are on opencores.org for years, thousands of downloads in the mean time, and it is just portable VHDL. And it was no pain to write. Compiles with stone-age ISE 10.1.

regards, Gerhard

Given the small way one opamp and four resistors can be connected, I'm certain that it's been done many times. But I re-invented it, based on the idea of linearizing a mediocre current source with negative resistance. One unconscious inspiration was probably making a fast linear ramp by charging a capacitor. A ramp can be curved upwards by applying a little feedback from an amplifier with a gain above 1. We do that in some products. A resistor to ground curves it the other way. Making an 8 ns ramp that's 10 bits linear is tricky.

I've done similar things, in ramps and RTD circuits and such, but I was thinking about it in a different way.

see Spehro's post for example... and I'm sure a

The RTD thing that Spehro mentioned is cool, but it's not a constant-current circuit. It deliberately increases the RTD current to correct for the platinum curve. It's like the thing I posted, but with a little more gain in the opamp.

No doubt it's been done before and may be in some literature somewhere. But nobody mentioned it here until I did, so it's fuel for discussion and maybe learning.

Why don't you toss in a new transimpedance circuit that we can discuss.

I have a really goofier one, even less parts and no matching issues. Or maybe two.

Cool. Provide a link.

Of course it's bait. This is an electronic design group. Design something.

We covered a whiteboard with lines yesterday, black lines for real signals, red for complex. Or the other way around; I can't recall.

You need a high IQ to keep up with this complex stuff.

The problem isn't so much the quantized z-domain Signals and Systems stuff, it's driving the horrible FPGA compiler tools. That's basically a full-time job.

Cast an eyeball at comp.arch.fpga. People spend more time trying to compile the logic than they spend architecting the logic.

Logic design is getting more abstract. The compilers do stuff like FIR filters at high level. One sometimes has to really dig to find out what the actual gate-and-flop logic actually is. Sometimes you have to fight the tools from optimizing out stuff that you really want to be there. It's like having to read the assembly language to see what the C compiler is doing.

Soldering and scoping parts is fun now and then. I'd hate to quit doing that.

Axibus presents multiple ports between the ARM and the fabric. Each port has a handshake and a transaction ID, sprt of a file handle concept. For a write, there are write address ports, write data ports, and write handshake ports. The address and data can be posted in any order, and the fabric logic has to verify that the IDs match.

Axi Lite simplifies things down to a mere 5 ports and hides the IDs. But it's still a potential buggy hairball (which cost us 3-4 weeks of designer time) that can crash Linux.

We had to take over and design a very deliberate post-bus-state machine to make it work.

This isn't your father's address/data/read/write bus.

The Xilinx projects seem to burn twice the hours as compared to the Altera ones.

One acquired skill among pro FPGA designers is learning to ignore hundreds of compiler warnings.

Hey, I have to pay for all that mess.

Do a Vivado design maybe. Something complex.

More time coding the test bench means that not enough time was spent coding the code. Or that people can't force the code to be right in the first place.

I just can't understand how someone who is otherwise competent and capable is so psychologically needy. You literally can't live without either ego aggrandizement or pointless arguing with everyone here. I don't have a clue as to how you survive in the real world.

Spoken like a true newbie. Warnings from compiling the HDL normally indicate you are doing something wrong that may not be fatal. Warnings during place and route often indicate the tools added logic that isn't used, for example, the carry output of an adder which isn't connected... or that you have problems in your code. If you get lots of warnings you need to consider your approach... or consider other tools.

You didn't do your due diligence. You were sucked in by the Xilinx marketeers. So complain to your management who let that happen.... who is that again?

Lol, I'm sorry, but you don't need to use crappy tools to design something complex. The design is what determines if it is complex, not the quality of the tools you select to do it.

I find it funny that when you started you Zedboard project you were singing praises of how great the concept was. Now you are bemoaning the crap tools you had to use which you had no choice on because they are the *only* way to use the Zynq parts. Did the Zynq part really do anything for you a separate FPGA and ARM part couldn't do? Oh yeah, I forgot, for a hardware guy you don't want anyone to have to design hardware unless it involves purely analog components. lol

BTW, has anyone pointed out to you that these days a *lot* of digital interconnect has to be designed with knowledge of the analog behavior? Is that too hard for you?

Lol! You really don't know what you are talking about. Not an f'ing clue. I'll channel some guy with the initials JL and ask you to show us the HDL code you've written lately. Clearly anyone who understands the process as well as you do must have written tons of HDL and had it all work the first time.

Or I could say you are exactly right... people can't force the code to be right in the first place. No one can.

It was cold the morning that Challenger was launched. The Thiokol engineers were concerned about the SRB o-rings and advised against launch until it warmed up. Management overrode them.

Negligent homicide, at least.

" Bob Ebeling from Thiokol delivered a biting analysis: "[W]e're only qualified to 40 degrees ...'what business does anyone even have thinking about 18 degrees, we're in no man's land.'"

That's silly. There is no power available here.