A good video about decoupling capacitors

Bit thin skinned are you? You're quite happy to derogate others in this group - expect the same in return.

Do you drive screws in with a hammer?

But if it's just going to be treated as a lumped-element circuit I don't get what makes 50 ohm source and load terminations special. In the sim the 4x 100n RLC circuit shunted by 25 ohms equivalent Thevenin resistance has a crazy-deep resonance at about 20 MHz because its Q is crazy high with that resistance, the phase goes from -90 to 90 in an instant and stays at 90 degrees forever.

Videos have their purpose, but good articles and references are better.

Trump university uses osmosis.and, sometimes, genetics.

RL

Actually, I'm autistic and don't much care what people think about me. But "load of bollocks" has minimal technical content.

Rarely, although I do enjoy a bit if irony when available.

What's your real name?

Got thoughts on that?

Better to measure real parts on real boards. That can be very different from sims.

As Gerhard mentioned even 10 100n in parallel is still high impedance off the main resonance, and I think the reason we're still at circa

-60dB at say, 50 MHz on the chart here:

at 8:47 is due to the 25 ohm in shunt from the VNA.

But my VRM small-signal output impedance is hopefully not 50 ohms at 50 MHz unless I get very unlucky and hit on a resonance of its output network. So why are we driving these model circuits with 50 ohms down there.

Not trying to be obtuse I'm just not sure what that graph is supposed to represent with respect to real world decoupling circuits. It looks like from the graphs he's trying to say that 4x 100n has a low small signal impedance out to daylight I don't buy that, not with a low source resistance. But perhaps I'm misinterpreting the test results.

A low frequency analyzer seems a more appropriate tool for the job but a new Keysight E4990A with a bandwidth of 100 MHz is only $87,000 so, yeah.

A real PCB will usually have power pours on layers adjacent to ground planes, seeded with bypass caps and lots of vias everywhere. That behaves nothing like some little 50-ohm microstrip perf board with a few caps inline and SMA connectors on both ends. Nothing.

My favorite analysis tool is a coax connector snooping that plane voltage, into a fast oscilloscope. That cuts through a lot of theory.

On 9/2/25 5:13 PM, john larkin wrote: <...>

Right. But if I were buying a spectrum analyzer, I'd prefer one that went down into audio frequencies too.

Bode 500 goes from 10mHz to 450MHz:

I have a Bode 100, 1Hz to 50MHz, best instrument I ever owned:

Good old HP 4395A goes from 10Hz to 500MHz. And it is VNA/SA/Impedance Analyzer in one. Have one on my desk.

Okay, so those smaller board connectors are going to introduce smaller parasitics into the circuit than SMA ones, but it just seems to me you're going to end up disappearing up your own butt with this kind of thing if you take it too far and get a wholly inaccurate picture of what's going on. At the multi-Ghz frequencies that you and others are working at these days, you might be introducing instability *or* eliminating it simply by your trying to measure it. You would need to somehow remove the effects of your snooping connector and whatever scope it goes to from your measurements. So how are you going to accurately do such de-embedding to arrive at meaningful results you can have confidence in?

A 50 ohm coaxial snoop wouldn't much change the waveforms on a hunky power pour.

When we want to snoop a logic level without trashing it, we use a 450 ohm resistor and then the coaxial connector. That forms a 10:1 probe into the cable and a 50 ohm scope. A good fast CMOS or ECL logic signal won't much notice a 500 ohm load.

Fast fet probes are good, especially when we don't have a coax on the board.

Am 03.09.25 um 19:58 schrieb john larkin:

Hard to understand? The stripline board is for characterizing the _capacitors_. If your board is different, he results will be different; but no amount of copper copper pour can make up for wrong capacitors. For the first 50 ps maybe, until the plane is empty 0.5" around the chip. Separate things need to be tested separately. Divide et impera!

EM-Simulation is also part of the picture. That's what ADS, Genesys, CST or HFSS are for.

And I had SMA testpoints on my boards in 1984, such as <

I did not exclude that. Here it's 54752A / 54754A <

or 89441A for DC & slow, to 2.6 GHz.

BTW I have written a C program to control the 89441A via LAN. One can simply open port 5002 on 192.168.xy.zzy and feed it with GPIB bus commands. BNC LAN option required + Amazon BNC to rs-45 converter box. I use Linux / gcc, source available.

cheers, Gerhard

And its own non-trivial impedances.

A power system needs to be tested all together. The planes, the dielectrics, the skin loss, the vias, the stackup, the caps all interact.

With decent size pours, plane capacitance is the fast bypass and vias are important impedances. After that, most any uF-range ceramic caps work fine.

Picotest has injection amplifiers, maybe they could be used

Yikes. $2000. And only 1 amp and 20 ns.

The best current injector is the real stuff on the board.

I sometimes TDR a test trace much like yours.

I see appnotes where some slow thing is being tested and someone pontificates about the evils of right-angle traces and the need to bevel or better yet curve traces. I've never absolutely seen a 90 degree bend on a 50 ohm microstrip, with a 30 ps TDR. I can see vias.

Particularly if you don't bother to put series inductances, series resistances and parallel capacitances into the the parts you simulate.

Parasitic elements can be a nuisance - sometimes a game changer.