1ns max jitter oscillator, cheap - for fast 4 diode sampler

I guess the assumption we're working with here is that there are two oscillators, one with low distortion/broadband noise but higher phase noise, like a Wien bridge, and the other with better phase noise but higher distortion/broadband noise like from a cheapo frequency synthesizer. So through locking they ideally compensate for each other's deficiencies.

At least that seems to be the thrust of the Analog Devices whitepaper on the technique that GH posted. If you don't care about distortion or broadband noise then I suppose it's irrelevant to have o2, but recall that initially I was unsure of the purpose of the required oscillator I thought it might be for testing the performance of the sampler/ADC rather than clocking.

John Larkin wrote in news: snipped-for-privacy@4ax.com:

these?

MEMS oscillators are low jitter.

I wonder how noisey MEMES oscillators are... :-)

e:

ally at square one

. RC typically have 1us of jitter (found info on the web), and a crystal os cillator, standard type probably 1ns jitter. But I think that idea was craz y, a PLL clean up, would not work I guess.

uld do many samples and average), I would guess I need jitter of 300ps (10% ) of my 3ns reolution)

th low price in mind)

some RF|microwave transistor - HFA3134, BFR92A etc?

Somewhere else in the thread, an LC oscillator was mentioned. I suggested m aybe a Colpits. That is close to what you are suggesting, right?

Cheers

Klaus

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I am totally at square one

e jitter. RC typically have 1us of jitter (found info on the web), and a cr ystal oscillator, standard type probably 1ns jitter. But I think that idea was crazy, a PLL clean up, would not work I guess.

ow (I could do many samples and average), I would guess I need jitter of 30

rt? (with low price in mind)

ebase

ns are

per

for reflected pulse. Since I need up to 200m lenth, the maximum time from the emitted pulse to reflected is 3us. So if the jitter is slowly changing over time, it may be a lot less in only that time span.

C,

t over 2 USD which is a lot more expensive than a picosecond timing PWM mic rocontroller

the receiver thresholds (100mV)?

You could probably do a slow calibration routine with the DAC with interval s, so thermal drifts effects are calibrated out

Cheers

Klaus

What sort of thermal drift in offset voltage does the SN65LVDS2DBVR have? Perhaps that's a question for JL.

Or any injection that doesn't have much above F_0. The "whack" in square wave injection comes from the series of odd harmonics, but the actual locking is achieved by the F_0 component.

Clifford Heath.

Injection locking can be done a lot more gently using parametric effects.

Cheers

Phil Hobbs

Something needs to be nonlinear, which would usually be the natural amplitude limiting mechanism. In a very linear circuit, with a really good AGC loop to regulate amplitude, injection locking gets interesting.

I played with a polyphase phase-lock idea, to start an oscillator and have it lock to a reference at multiple phase opportunities. That could be done a number of ways, including injection. Fun but not good enough.

The 'gentle' locking wouldn't give a square-wave clock, would it? For sampling, you don't really WANT a sinewave (zero cross detection would be a jitter source), but a harmonic-rich signal with sharp transitions (and well-defined transition times).

Presumably, too, your timebase needs aren't profound in terms of spectral purity. Sines could be good for timing accuracy, but not well-adapted to the sample-time requirement of an abrupt edge.

A good overall solution is a squarewave delay-line oscillator with a second oscillator as a backup. One such can be taking trigger events and producing samples, while the backup is internally gated for a calibration. Every few seconds, swap the roles, so you always have a freshly calibrated timebase.

Regular old CAT5 might not age well as a time standard, but it's an acceptable delay line (if a TDR can find a break down to a few inches, the timing jitter must be subnanosecond for the delay). There are other kinds of delays (piezoelectric/glass-plate like PAL used to use) but not as easy to damp (terminate) between triggers.

It's not essential to control the timing accurately, just precisely; accuracy can be calibrated in as required.

The high Q resonators that give stable clock frequencies and good long term jitter only have a high Q at a particular frequency.

If you want to get a square wave clock out of that you have to use a comparator to square it off, with all the added extra noise that that introduces.

Tough.

Both of them are low Q oscillators. No amount of calibration is going to make them any quieter.

High frequency crystal-based oscillators can offer jitter down to about 125 femtoseconds. That's hard to beat.

True, but high-Q oscillators do offer precision and stability.

A delay line has resistor noise associated with its impedance, is that the unquiet aspect? Or, it's higher (due to skin effect) for the highest harmonics? The stored-energy model of Q doesn't really clearly fit the delay-line with square waveform. The jitter comes not from the fundamental, but from sums of harmonics, so the appropriate energy-input per cycle and stored energy are difficult to infer.

Starting in phase, though, is impossible for a high-Q quartz crystal (and rather difficult for an LC tank). The various time-vernier schemes have the same jitter as a monostable (not very good); and the track-hold trick with multipliers is elaborate and awkward.

whit3rd wrote: [...]

Not true. Thermal noise is associated with dissipation, loss. The characteristic impedance of a transmission line is not lossy and therefore does not generate noise.

Delay line resonators can have respectable Q values, somewhere between LC and quartz crystals.

This being usenet, and before anyone jumps on me, I'll add that the *loss* of practical transmission lines *does* produce thermal noise.

Jeroen Belleman

completely right. cheers, Gerhard

The timing scheme we used back in 1988 interpolated between 1.25 nsec spaced clock edges. We actually ramped over about 2nsec, and the time jitter was correspondingly small.

Smaller than the 60psec on the clock (which was dire, and would certainly have been improved if we'd ever got to put the machine into production).

When I reworked the design - for another application nearly ten years later - I could buy a thinned-crystal based oscillator with about 1psec jitter.

Back 1988 we were thinking hopefully about a SAW oscillator, but we would have had to buy a small batch of them, and the prototype machine didn't need particularly wonderful jitter performance.

Coaxial ceramic resonators are short, high dielectric, usually shorted transmission lines. The lower frequency parts (below say 1 GHz) have Qs in the hundreds, and the higher ones in the thousands. Temperature stability is astounding.

CCR characteristic impedances are low, ca 10 ohms, and their DC resistances are milliohms. Like most RF parts, they are characterized in frequency domain, but they really are transmission lines.

Higher harmonics generally have lower Q, so delay line oscillators tend to settle down to making sine waves.

It's tough for the crystal because it's a complex mechanical device with weak coupling to the outside world. The LC instant start is trivial; first semister EE or calculus.

HP sold a digital delay generator, for a while, that instant-started a quartz crystal oscillator. It was ugly.

You can do zero-cross detection by amplifying and clipping.

The math of injection locking is fascinating--it's full of bifurcations and limit cycles and stuff. Sure works if you get it right, though.

Cheers

Phil Hobbs