1ns max jitter oscillator, cheap - for fast 4 diode sampler

Or just lower the charge voltage and linearise the exponential charge curve in software. Longer delay -> less dV/dt -> less accurate.

In our products, we compute a polynomial at factory cal time to linearize the dac codes going into the ramp comparator. The poly terms go into a cal table. That's why we can use an RC instead of a current source.

We use a Keysight time interval counter to cal the ramps.

It takes a bit of care to avoid "stitching errors", little hickies every time we add one digital count and jump the ramp back down.

Resistors are cheap and very wideband. Fast precision current sources are a real pain. The curvature is small, and a 2nd or 3rd order polynomial onto the DAC data calibrates things nicely.

I don't get where this idea come from that the Wien bridge topology is intrinsically low Q. Is it because the open-loop RC network is?

The amplifier in the circuit is not just a power buffer to overcome loss like e.g. a Colpitts oscillator or phase-shift oscillator. Look at which terminal the frequency-selective network is connected to, y'all.

Precision might be, but running through a calibration procedure (which might take a millisecond, most of it devoted to engaging a microprocessor and turning it off again afterwards) every minute would let you get away with something cheap and practical.

That's one approach. If you want to exploit the full precision of the DAC, a linear ramp makes best use of it.

The asynchronous slick way to do that (we've discussed it in the past) is with a sine/cosine quadrature master oscillator (which can be quartz-locked) and track/hold amps that go into HOLD at the trigger time, with multiplier/summer circuitry.

sin(w*t -phi) = sin(w*t) cos(phi) - cos(w*t) sin(phi) after you engage the HOLD, and sin(w*t - w*t) = 0 = sin(w * t) cos(w * t) - cos(w * t) sin (w * t) before (with the track/hold amplifiers tracking the sine and cosine of the master clock).

Just like the picture, output goes from flat zero to full sinewave in an instant.

Gilbert cells and transformer adders can do the job at a wide range of frequencies.

That's not what I meant. When you start the LC oscillator, there is a random phase between the trigger and the XO. How do you measure that?

Wien relies on the cancellation of two RC phase-shift networks. Both the R's are noisy, so how can the result *not* be noisy?

In a good LC, the resistance is far less than 1% of the reactances.

Start a ramp at the trigger instant. Let it ramp up until the next clock edge but one, stop it, and digitise the static voltage that the ramp settled at.

Waiting for at least one clock interval gets past the mess as the ramp gets under way.

Back in 1990 we did it with an 800MHz clock and divided up the 1.25nsec clock into 10psec intervals.

It took about 40nsec for the digitised interval to come available, and we had to recalibrate the ramp generator every few minutes - one DAC set the ramp starting voltage, and another the ramp slope - but that took less than a millisecond.

The system had a pair of timing boards which could also generate edges timed to 10psec between clock edges which made self-calibration tolerably straight-forward.

Um do you know what Q is? > intrinsically

Which ones? I haven't seen it used on a chip.

because they are big, which means the chips use more area on the wafer and cost more money to make. They do use inductors on chips, begrudgingly, when they want a low phase-noise oscillator, because LC oscillators have better phase noise than RC oscillators, and because people will pay enough more money for this good phase noise performance that it justifies the increased cost of the silicon that is occupied by the big inductor. I have designed the local oscillator of a cellphone radio chip, and yes it used an LC oscillator, like all of our competitors also did.

It is difficult to convince people about things like phase noise, because most people lack the equipment to measure it easily, and because LTSpice won't simulate it. You need something a bit more spendy, like SpectreRF.

I also find it impossible to convince people that their mixer won't work better with a low-distortion sine wave LO signal than it would with a nice sharp square wave LO. Again, hard to simulate the noise performance properly with anything cheap, and the people who know how to measure it are not the ones who need convincing.

Thanks for that Gerhard... we love you anyway. :^)

George H. (who can never remember how to spell Wien.)

Huh? There's no energy storage.. I haven't tried this, but if you turn off the power, I'd guess the oscillations die away right away. Low Q. (I've used Wien bridge oscillators with diode AGC and they turn on and off right away.)

George H.

Right, Q is a measure of energy storage. How much energy leaks out of the oscillation amplitude during each cycle.

George H.

That question is probably going to come too close to the area you don't want to talk about. How about a different approach.

Instead of trying to lock a pll to an oscillator at random phase, we could measure to time between an asychronous trigger and an XO clock:

1. start a fast ramp at the trigger
2. find the delay to the second clock pulse from the XO
3. store this in a sample/hold or adc
4. count to the target delay minus 1 clock
5. start a fast ramp to the same delay time as the original

You now have the target delay locked to the XO but shifted in time

1. add the desired vernier delay to fill in between clock periods

There is the nasty problem of the trigger hitting exactly on a clock transition, but that will occur with any asynchronous system. I am now examining patents from Tektronix, LeCroy, HP/Agilent/Keysight to find out how they handle the problem.

It's a weird digital PLL. A fast ADC is clocked based on the XO and digitizes the triggered oscillator waveform. A mess of math in an FPGA figures out the phase difference, does some PID control stuff, and drives a DAC and a varicap to trim the LC oscillator. Lots of fun signals-and-systems-Nyquist-sampling-theorem-control-theory stuff.

HP did something similar ca 1970, but used a vernier heterodyne trick. That takes longer to measure the difference and close the loop, and jitter piles up until then.

There's a discussion of various digital delay generator architectures in Wikipedia. I had to write it to get them to footnote my company name; they insisted on a contribution of content.

That's why we waited for the third clock edge, or the second clock edge after the first clock edge that was actually after the trigger pulse had been detected and registered.

Nothing nasty about it, but it is one more delay (but nowhere near as long as the ramp sampling process)

That's what we did back in 1990. anyway, and it did work, even if the machine never went into production.

Which ICs?

Keep in mind that OP asked for "low cost" as well so it doesn't sound to me like he was asking for a low phase noise 2GHz sampling clock - I'm no expert or nothin' but I don't think anything about a system like that would fit my own definition of "low cost."

While it may not be an appropriate solution for this particular project my point was that CD made the Wien bridge suggestion and people jumped down his throat like it was the dumbest idea in the world; my counter-point was, not so fast, the Wien topology actually can be pretty good with respect to phase noise. And at single or tens of MHz it actually is used for low-jitter sampling clocks, to avoid using impracticably large inductors or off-chip crystals.

In essence my contention is that while it might indeed be an inappropriate choice for this particular project it isn't for the reasons that were given.

A good number of papers in the literature about design of on-chip low phase noise Wien bridge clock oscillators:

A patent by Infinenon:

For clocks in the 100s of kHz to several MHz range the topology seems to have a lot of nice properties, since unless you want to use off-chip Ls or crystals your options are rather limited.