About the top clock frequency that you can go through a backplane of useful size is about 500 MHz. The propagation speeds eat you alive, not to mention skew, especially at wide transaction widths (say 256 bits). I figure they use a multiplicity of busses, at least 1184 but not more than 2368 signals was it? And going differential gets you higher clocks but with worse skew problems. Does re-aggregating several very high speed serial signals (10,000 MHz each) back to a parallel form do the job often enough to help?